HARDWARE SECURITY FOR AN ELECTRONIC CONTROL UNIT
First Claim
1. A vehicle electronic control unit, comprising:
- a main processor configured to process tasks assigned to the electronic control unit;
a memory to store vehicle data for use by the main processor;
a security processor configured to encrypt and to decrypt data from the memory for use by the main processor, the security processor executing encryption and decryption in hardware circuitry that is field programmable, the security processor being configured to encrypt and decrypt in parallel to the main processor; and
a substrate in which is defined a bus to connect the main processor, the memory, and the security processor.
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Accused Products
Abstract
An electronic control unit (ECU) for vehicles is described, including memory to store encrypted data and unencrypted data; a main control unit operatively connected to memory to access unencrypted data; and a hardware encryption-decryption device operatively connected to memory to access encrypted/decrypted data for decryption using a hardware algorithm and for encryption using a hardware algorithm. Data in the memory is decrypted by the hardware encryption-decryption device using the hardware algorithm and stored in memory for use by the main control unit. Data in memory is encrypted by the hardware encryption-decryption device using the hardware algorithm for storage in memory. The main control unit and the hardware encryption-decryption device are separate integrate circuits on a same substrate or SOC and are connected by a bus and can process data in parallel. An external bus can communicate encrypted information with the ECU to allow encrypt/decrypt at run time (on-the-fly) and wire-speed.
48 Citations
25 Claims
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1. A vehicle electronic control unit, comprising:
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a main processor configured to process tasks assigned to the electronic control unit; a memory to store vehicle data for use by the main processor; a security processor configured to encrypt and to decrypt data from the memory for use by the main processor, the security processor executing encryption and decryption in hardware circuitry that is field programmable, the security processor being configured to encrypt and decrypt in parallel to the main processor; and a substrate in which is defined a bus to connect the main processor, the memory, and the security processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. An electronic control unit, comprising:
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a memory to store encrypted data and unencrypted data; a main control unit operatively connected to the memory to access unencrypted data; and a hardware encryption-decryption device operatively connected to the memory to access encrypted data for decryption using a hardware algorithm and to access decrypted data for encryption using the hardware algorithm; wherein data in the memory is decrypted by the hardware encryption-decryption device using the hardware algorithm and stored in the memory for use by the main control unit, wherein data in the memory is encrypted by the hardware encryption-decryption device using the hardware algorithm for storage in the memory by the hardware encryption-decryption device, and wherein the main control unit and the hardware encryption-decryption device are separate integrated circuits on a single substrate with a bus connecting the memory with the main control unit and the hardware encryption-decryption device and process data in parallel. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification