SAFETY FEATURES FOR HIGH LEVEL DESIGN

• US 20180218094A1
• Filed: 03/29/2018
• Published: 08/02/2018
• Est. Priority Date: 11/02/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Titley, Adam
• Granted Patent: US 10,366,190 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

Aspects of this disclosure relate generally to electronic design automation, and more specifically, to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. Some innovative aspects can be implemented in computer-readable media, systems and methods capable of accessing an algorithmic description representation of a circuit design. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. The media, systems and methods also are capable of compiling the algorithmic description representation of the circuit design. In some implementations, the compiling includes identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Claims

1. Tangible computer-readable media storing non-transitory code executable by one or more processors, the code being configured to, when executed by the one or more processors, cause operations to be performed including:

accessing an algorithmic description representation of a circuit design, the algorithmic description representation being specified in a first language and including at least one programming language construct associated with a first safety data type; and

compiling the algorithmic description representation of the circuit design, the compiling including;

identifying the at least one construct,

accessing a first safety data type definition associated with the first safety data type, and

generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition, the second representation being provided in a second language and including at least one safety feature for a portion of the circuit design associated with the at least one construct.

2. The media of claim 1, wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.

3. The media of claim 1, wherein the first language is an OpenCL-compatible programming language.

4. The media of claim 1, wherein the second representation of the circuit design is a register-transfer level (RTL) representation.

5. The media of claim 1, wherein the algorithmic description representation includes one or more directives identifying one or more header files, the one or more header files defining one or more safety data types including the first safety data type.

6. The media of claim 5, wherein the compiling further includes:

identifying the one or more directives;

identifying the one or more header files;

accessing the one or more header files;

retrieving the contents of the one or more header files; and

including the contents of the one or more header files in the algorithmic description representation prior to generating the second representation.

7. The media of claim 1, wherein the at least one construct includes at least one variable defined using the first safety data type.

8. The media of claim 1, wherein the at least one construct includes at least one function having a return type defined using the first safety data type.

9. The media of claim 1, wherein the at least one construct includes at least one function including at least one parameter defined using the first safety data type.

10. The media of claim 1, wherein the at least one construct includes at least one pragma directive identifying a function as a safety-critical function.

11. A system comprising:

one or more memory devices storing non-transitory processor-executable code configured to implement instructions;

one or more processing devices to execute the processor-executable code to implement the instructions, the instructions configured to cause operations to be performed including;

accessing an algorithmic description representation of a circuit design, the algorithmic description representation being specified in a first language and including at least one programming language construct associated with a first safety data type; and

compiling the algorithmic description representation of the circuit design, the compiling including;

identifying the at least one construct,

accessing a first safety data type definition associated with the first safety data type, and

generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition, the second representation being provided in a second language and including at least one safety feature for a portion of the circuit design associated with the at least one construct.

12. The system of claim 11, wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.

13. The system of claim 11, wherein the algorithmic description representation includes one or more directives identifying one or more header files, the one or more header files defining one or more safety data types including the first safety data type.

14. The system of claim 13, wherein the compiling further includes:

identifying the one or more directives;

identifying the one or more header files;

accessing the one or more header files;

retrieving the contents of the one or more header files; and

including the contents of the one or more header files in the algorithmic description representation prior to generating the second representation.

15. The system of claim 11, wherein the at least one construct includes at least one variable defined using the first safety data type.

16. The system of claim 11, wherein the at least one construct includes at least one function having a return type defined using the first safety data type.

17. The system of claim 11, wherein the at least one construct includes at least one function including at least one parameter defined using the first safety data type.

18. The system of claim 11, wherein the at least one construct includes at least one pragma directive identifying a function as a safety-critical function.

19. A method comprising:

accessing, by a computer system, an algorithmic description representation of a circuit design, the algorithmic description representation being specified in a first language and including at least one programming language construct associated with a first safety data type; and

compiling, by the computer system, the algorithmic description representation of the circuit design, the compiling including;

identifying the at least one construct,

accessing a first safety data type definition associated with the first safety data type, and

generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition, the second representation being provided in a second language and including at least one safety feature for a portion of the circuit design associated with the at least one construct.

20. The method of claim 19, wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.