APPARATUSES AND METHODS FOR DISTRIBUTING ROW HAMMER REFRESH EVENTS ACROSS A MEMORY DEVICE

• US 20180218767A1
• Filed: 01/30/2017
• Published: 08/02/2018
• Est. Priority Date: 01/30/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: WOLFF, GREGG D.
• Granted Patent: US 10,490,251 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.

Claims

1. An apparatus comprising a first chip including a first memory array and a second chip including a second memory array;

wherein a first refresh command is supplied in common to the first chip and the second chip to cause a first chip to perform a first refresh operation on a plurality of first memory cells in the first memory array and the second chip to perform a second refresh operation on a plurality of second memory cells in the second memory array, the plurality of first memory cells being different in number than the plurality of second memory cells.

2. The apparatus of claim 1, wherein a second refresh command is supplied in common to the first chip and the second chip to cause the first chip to perform a third refresh operation on a plurality of third memory cells in the first memory array and the second chip to perform a fourth refresh operation on a plurality of fourth memory cells in the second memory array, the plurality of third memory cells being different in number than the plurality of fourth memory cells.

3. The apparatus of claim 2, wherein the first refresh command is issued a plurality of times at first intervals, the second refresh command being issued a plurality of times at second intervals, and the first intervals being equal to the second intervals.

4. The apparatus of claim 2, wherein a third refresh command is issued in common to the first chip and the second chip to cause each of the first chip and the second chip to perform a fifth refresh operation on each of a plurality of fifth memory cells in the first memory array and a plurality of sixth memory cells in the second memory array, the plurality of fifth memory cells being equal in number to the plurality of sixth memory cells.

5. The apparatus of claim 4, wherein the first refresh command is issued a plurality of times at first intervals, the second refresh command being issued a plurality of times at second intervals, the third refresh command is issued a plurality of times at third intervals, and the first intervals being equal to the second intervals and different from the third intervals.

6. The apparatus of claim 2, wherein the first chip comprises a first refresh address storing circuit configured to store a first address corresponding to the plurality of first memory cells in the first memory array, the second chip comprises a second refresh address storing circuit configured to store a second address corresponding to the plurality of fourth memory cells in the second memory array, and the first address and the second address being provided externally.

7. An apparatus, comprising:

a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation;

a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh commands with a row hammer refresh operation;

wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.

8. The apparatus of claim 7, wherein:

the first memory is further configured to execute a sequential refresh operation responsive to the second of the sequential refresh commands; and

the second memory is further configured to execute a sequential refresh operation responsive to the first of the sequential refresh commands.

9. The apparatus of claim 8, wherein:

the row hammer refresh operation executed by the first memory refreshes fewer memory cells than the sequential refresh operation executed by the first memory; and

the row hammer refresh operation executed by the second memory refreshes fewer memory cells than the sequential refresh operation executed by the second memory.

10. The apparatus of claim 7, wherein:

the first memory is a member of a first group of memories, wherein each memory of the first group of memories is configured to replace the first of the sequential refresh commands with a row hammer refresh operation; and

the second memory is a member of a second group of memories, wherein each memory of the second group of memories is configured to replace the second of the sequential refresh commands with a row hammer refresh operation.

11. The apparatus of claim 7, further comprising:

a controller coupled to both the first and second memory devices and configured to issue the sequential series of refresh commands to the first and second memory devices;

wherein

the first memory device is enabled to replace the first of the sequential refresh commands with a row hammer refresh operation when the first memory device possess a token and the second memory device does not possess the token; and

the second memory device is enabled to replace the second of the sequential refresh commands with a row hammer refresh operation when the second memory device possess the token and the first memory device does not possess the token.

12. The apparatus of claim 11, wherein the controller is further configured to pass the token between at least the first and second memory devices and comprises an N-bit shift register coupled to a token bus that provides the token to at least the first and second memory devices.

13. The apparatus of claim 11, wherein the first memory device comprises:

an address counter circuit configured to output a series of internal memory addresses responsive to a refresh command received from the controller;

a row hammer refresh counter coupled to the address counter and configured to receive the token, the row hammer refresh counter further configured to stall the address counter on a row hammer refresh event;

wherein the row hammer refresh counter stalls the address counter only when the row hammer refresh circuit possesses the token.

14. The apparatus of claim 13, wherein the row hammer refresh counter receives at least a portion of the internal memory addresses as input, the row hammer refresh counter configured to the trigger row hammer refresh operation based on the at least a portion of the internal memory addresses.

15. A method, comprising:

receiving a series of refresh commands from a controller at a memory;

calculating, by the memory, a time in which to replace a refresh command with a row hammer refresh operation; and

delaying execution of the row hammer refresh operation until the memory receives a token from the controller.

16. The method of claim 15, further comprising:

executing, by the memory, a sequential memory refresh operation responsive to a refresh command from the controller when a row hammer refresh operation is not executed.

17. The method of claim 16, wherein the memory refreshes fewer memory cells when the memory executes row hammer refresh operation than when the memory executes a sequential refresh operation.

18. The method of claim 15, wherein the controller provides the token to at least one other memory when the controller does not provide the token to the memory.

19. The method of claim 18, wherein the operation of calculating a time in which to replace a refresh command with a row hammer refresh operation includes calculating the time once during a refresh cycle.

20. The method claim 19, wherein the memory is a member of a group of memories, wherein each memory of the group of memories is configured to replace a refresh command with a row hammer refresh operation once during a refresh steal cycle.