SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

• US 20180218950A1
• Filed: 03/27/2018
• Published: 08/02/2018
• Est. Priority Date: 04/11/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CANTORO, MICRO, TOLEDANO LUQUE, MARIA, HEO, YEONCHEOL, BAE, DONG IL
• Granted Patent: US 10,453,756 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02612 Formation types
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 : with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element

Abstract

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming an active pattern on a substrate; and

forming a gate electrode intersecting the active pattern, the gate electrode extending in a first direction,

wherein the forming of the active pattern comprises;

forming a lower pattern and a pair of channel patterns on the lower pattern,

wherein the lower pattern includes a first semiconductor material,

wherein each of the pair of channel patterns includes a second semiconductor material different from the first semiconductor material,

wherein a first portion of the gate electrode is disposed between the pair of channel patterns, and

wherein a width of the first portion of the gate electrode, measured along the first direction, decreases in a direction away from the substrate.

2. The method of claim 1, wherein the forming of the lower pattern and the pair of channel patterns comprises:

forming a preliminary active pattern on the substrate, the preliminary active pattern including the first semiconductor material; and

oxidizing exposed sidewalls of the preliminary active pattern.

3. The method of claim 2, wherein the oxidizing of the exposed sidewalls of the preliminary active pattern comprises oxidizing the first semiconductor material included in the preliminary active pattern to form an oxide layer.

4. The method of claim 1, wherein the pair of channel patterns are spaced apart from each other in the first direction, and

wherein the gate electrode is formed surrounding both sidewalls and a top surface of each of the pair of channel patterns.

5. The method of claim 1. wherein the first semiconductor material is silicon and the second semiconductor material is germanium.

6. A method for manufacturing a semiconductor device, comprising;

forming a base pattern protruding from a substrate;

forming a semiconductor layer covering the base pattern;

oxidizing the semiconductor layer to form an oxide layer, and forming a channel semiconductor layer between the oxide layer and the substrate and between the oxide layer and the base pattern;

patterning the channel semiconductor layer to form a pair of channel semiconductor patterns on opposing sidewalls of the base pattern; and

removing a portion of the base pattern disposed between the pair of channel semiconductor patterns to form an active pattern, the active pattern comprising the pair of channel semiconductor patterns,

wherein the base pattern includes a first semiconductor material, and

wherein the semiconductor layer includes the first semiconductor material and a second semiconductor material different from the first semiconductor material.

7. The method of claim 6, wherein the oxide layer includes an oxide of the first semiconductor material, and

wherein the second semiconductor material is concentrated on the oxide layer or at a side surface of the oxide layer to form the channel semiconductor layer when the oxide layer is formed.

8. The method of claim 6, wherein the oxidizing of the semiconductor layer comprises performing an oxidation process cycle at least once,

wherein the oxidation process cycle comprises an oxidation process and a thermal treatment process, and

wherein the oxidation and thermal treatment processes are sequentially performed.

9. The method of claim 6, wherein the forming of the base pattern comprises:

forming a mask pattern on the substrate; and

etching an upper portion of the substrate using the mask pattern as an etching mask to form a pair of trenches adjacent to the base pattern.

10. The method of claim 9, wherein the mask pattern remains on a top surface of the base pattern after the formation of the trenches, and

wherein the semiconductor layer is formed to cover a top surface of the mask pattern.

11. The method of claim 10, wherein the channel semiconductor layer comprises:

a first portion formed in the substrate and facing the oxide layer, wherein at least a part of the first portion does not overlap the base pattern;

a second portion formed in the base pattern adjacent to a side of the oxide layer; and

a third portion formed between the oxide layer and the mask pattern,

wherein at least a part of the second portion overlaps the mask pattern.

12. The method of claim 11, wherein the patterning of the channel semiconductor layer comprises performing an anisotropic etching process on an entire top surface of the substrate,

wherein, during the anisotropic etching process, the oxide layer and the first and third portions are completely removed but the second portion remains in place, and wherein the second portion forms the pair of channel semiconductor patterns.

13. The method of claim 6, further comprising forming a liner layer covering the channel semiconductor patterns before the removing of the portion of the base pattern,

wherein the liner layer includes silicon nitride (RN), silicon carbonitride (SiCN), silicon-boron nitride (SiBN), or silicon-carbon-boron nitride (SiCBN).

14. The method of claim 6, wherein a width of the base pattern decreases as a distance with respect to a first surface of the substrate increases, the first surface of the substrate facing the base pattern.

15. A method for manufacturing a semiconductor device, comprising:

forming an active pattern, the active pattern comprising;

a lower pattern protruding from a substrate; and

a pair of channel patterns spaced apart from each other in a first direction on the lower pattern; and

forming a gate electrode intersecting the active pattern, the gate electrode extending in the first direction,

wherein the forming of the active pattern comprises;

forming a semiconductor layer including a first semiconductor material and a second semiconductor material on the substrate; and

performing an oxidation process to form an oxide layer of the first semiconductor material and to form a first layer on the oxide layer or at a side of the oxide layer, wherein the second semiconductor material is concentrated in the first layer,

wherein each of the pair of channel patterns includes at least a portion of the first layer.

16. The method of claim 15, wherein the forming of the active pattern further comprises sequentially etching the semiconductor layer and an upper portion of the substrate to form the lower pattern and a semiconductor pattern on the lower pattern before performing the oxidation process,

wherein the oxide layer is formed on opposing sidewalls of the semiconductor pattern, and

wherein the semiconductor pattern includes the first layer.

17. The method of claim 16, wherein the first layer is included in a pair of upper patterns, and

wherein the forming of the active pattern further comprises removing the semiconductor pattern that is disposed between the pair of upper patterns to expose a top surface of the lower pattern.

18. The method of claim 15, wherein the forming of the active pattern further comprises etching an upper portion of the substrate to form a pair of trenches at a boundary of a base pattern before the forming of the semiconductor layer,

wherein the semiconductor layer is formed to cover the base pattern,

wherein the oxide layer is formed to cover bottom surfaces of the pair of trenches and to cover a top surface and sidewalls of the base pattern, and

wherein the first layer is formed between the oxide layer and the substrate and between the oxide layer and the base pattern.

19. The method of claim 18, wherein the first layer is a channel semiconductor layer, and

wherein the forming of the active pattern further comprises:

patterning the channel semiconductor layer to form a pair of channel semiconductor patterns on opposing sidewalls of the base pattern; and

removing a portion of the base pattern disposed between the pair of channel semiconductor patterns to form a recessed base pattern.

20. The method of claim 19, wherein a top surface of the recessed base pattern is disposed between a top surface of one of the pair of channel patterns and the bottom surface of one of the pair of trenches,

wherein the lower pattern comprises:

the recessed base pattern; and

portions of the pair of channel semiconductor patterns disposed between the top surface of the recessed base pattern and the bottom surface of one of the pair of trenches, and

wherein the pair of channel patterns are disposed further away from a surface of the substrate that faces the pair of channel patterns than the top surface of the recessed base pattern.