METHOD, DEVICE AND SYSTEM TO PROVIDE CAPACITANCE FOR A DYNAMIC RANDOM ACCESS MEMORY CELL

• US 20180219012A1
• Filed: 09/25/2015
• Published: 08/02/2018
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LILAK, Aaron, MORROW, Patrick, MEHANDRU, Rishabh, NELSON, Donald W., CEA, Stephen M.
• Granted Patent: US 11,049,861 B2
• Time in Patent Office: Days
• CPC Class Codes: H10B 12/036 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/33 the capacitor extending under the transistor
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

Claims

1-25. -25. (canceled)

26. An integrated circuit comprising:

a substrate;

a memory cell including a first transistor comprising;

a first doped region disposed at least in part in or on a first side of the substrate;

a second doped region disposed at least in part in or on a first side of the substrate;

a gate disposed on the first side, the gate coupled to receive a signal and, responsive to the signal, to activate a channel between the first doped region and the second doped region; and

a capacitor coupled to accumulate charge based on activation of the channel, wherein the capacitor is further coupled to send the charge from the memory cell via a second side of the substrate, the second side opposite the first side.

27. The integrated circuit of claim 26, wherein the second doped region is disposed between the capacitor and the first side.

28. The integrated circuit of claim 26, wherein the second doped region is disposed on the first side, and wherein the second doped region surrounds the capacitor at the first side.

29. The integrated circuit of claim 26, the capacitor including a branch structure that extends to the second doped region in a direction perpendicular to the second side.

30. The integrated circuit of claim 26, the capacitor including a branch structure that extends in a direction parallel to the second side.

31. The integrated circuit of claim 26, wherein the capacitor includes a first conductive region, a second conductive region and a dielectric disposed between the first conductive region and the second conductive region, wherein the first conductive region forms one or more lobe structures extending between the first side and the back side.

32. The integrated circuit of claim 26, wherein the memory cell is a dynamic random access memory cell.

33. The integrated circuit of claim 26, wherein the transistor is a fin field effect transistor.

34. The integrated circuit of claim 26, the memory cell further comprising another capacitor coupled to accumulate other charge based on activation of the channel, wherein the other capacitor is coupled to the substrate via the first side or the other capacitor extends from the second doped region via the first side.

35. A method comprising:

forming a first transistor of a memory cell, including;

disposing a gate on a first side of a substrate; and

forming a first doped region and a second doped region in or on the first side of the substrate;

performing thinning to expose a second side of the substrate, the second side opposite the first side; and

after the thinning, forming a capacitor that extends in or through the second side, wherein the capacitor is coupled to accumulate charge based on activation of a channel between the first doped region and the second doped region, wherein the capacitor is further coupled to send the charge from the memory cell via the second side.

36. The method of claim 35, wherein the second doped region is disposed between the capacitor and the first side.

37. The method of claim 35, wherein the second doped region is formed on the first side, and wherein the second doped region surrounds the capacitor at the first side.

38. The method of claim 35, wherein forming the capacitor includes forming a branch structure that extends to the second doped region in a direction perpendicular to the second side.

39. The method of claim 35, wherein forming the capacitor includes forming a branch structure that extends in a direction parallel to the second side.

40. The method of claim 35, wherein forming the capacitor includes forming a first conductive region, a second conductive region and a dielectric disposed between the first conductive region and the second conductive region, the first conductive region including one or more lobe structures extending between the first side and the back side.

41. The method of claim 35, further comprising forming another capacitor of the memory cell, wherein the other capacitor is coupled to accumulate other charge based on activation of the channel, wherein the other capacitor is coupled to the substrate via the first side or the other capacitor extends from the second doped region via the first side.

42. A system comprising:

an integrated circuit including;

a substrate;

a memory cell including a first transistor comprising;

a first doped region disposed at least in part in or on a first side of the substrate;

a second doped region disposed at least in part in or on a first side of the substrate;

a gate disposed on the first side, the gate coupled to receive a signal and, responsive to the signal, to activate a channel between the first doped region and the second doped region; and

a capacitor coupled to accumulate charge based on activation of the channel, wherein the capacitor is further coupled to send the charge from the memory cell via a second side of the substrate, the second side opposite the first side; and

a display device coupled to the integrated circuit, the display device to display an image based on the charge sent from the memory cell via the second side.

43. The system of claim 42, wherein the second doped region is disposed between the capacitor and the first side.

44. The system of claim 42, wherein the second doped region is disposed on the first side, and wherein the second doped region surrounds the capacitor at the first side.

45. The system of claim 42, wherein the capacitor includes a first conductive region, a second conductive region and a dielectric disposed between the first conductive region and the second conductive region, wherein the first conductive region forms one or more lobe structures extending between the first side and the back side.

46. The system of claim 42, the memory cell further comprising another capacitor coupled to accumulate other charge based on activation of the channel, wherein the other capacitor is coupled to the substrate via the first side or the other capacitor extends from the second doped region via the first side.