ROBUST TRIMMING SCHEME FOR LOW POWER RC OSCILLATOR COMPATIBLE WITH HIGH TEMPERATURE OPERATION

• US 20180219535A1
• Filed: 02/02/2017
• Published: 08/02/2018
• Est. Priority Date: 02/02/2017
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lim, Chern Sia Phillip
• Granted Patent: US 10,454,460 B2
• Time in Patent Office: Days
• CPC Class Codes: H03B 2200/005 including measures to switch a capacitor
• CPC Class Codes: H03B 2201/0208 the means being an element with a variable capacitance, e.g. capacitance diode
• CPC Class Codes: H03B 5/24 active element in amplifier being semiconductor device H03B5/26 takes precedence
• CPC Class Codes: H03B 5/26 frequency-determining element being part of bridge circuit in closed ring around which signal is transmitted; frequency-determining element being connected via a bridge circuit to such a closed ring, e.g. Wien-Bridge oscillator, parallel-T oscillator
• CPC Class Codes: H03K 4/501 the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator

Abstract

In some embodiments, the present disclosure relates to a frequency generator having a resistor network and a capacitor network. The capacitor network has a plurality of capacitors connected in parallel with one another. A comparator is configured to output an oscillating voltage signal. An input of the comparator is connected to the output of the resistor network and the output of the capacitor network. A frequency testing circuit is configured to calculate a frequency of the oscillating voltage signal and determine whether the frequency is within a range of an expected frequency. The frequency testing circuit may also be configured to selectively connect a first plate of the plurality of capacitors to a non-varying voltage or to the input of the capacitor network to adjust a frequency of the oscillating voltage signal.

Claims

1. A frequency generator, comprising:

a comparator configured to output an oscillating voltage signal having a first frequency;

a RC network circuit coupled between an input and an output of the comparator, wherein the RC network circuit comprises;

a resistor network;

a capacitor network comprising a plurality of capacitors connected in parallel, wherein each capacitor of the plurality of capacitors comprises a first plate and a second plate; and

wherein a frequency testing circuit is configured to determine whether the first frequency is within a range of an expected frequency, wherein the frequency testing circuit is configured to selectively connect the first plate of some of the capacitors disposed in the capacitor network to a non-varying voltage and other capacitors disposed in the capacitor network to an input of the capacitor network when the first frequency is outside the range of the expected frequency.

2. The frequency generator of claim 1, further comprising:

an inverter having an input connected to an output of the comparator and an output connected to the input of the capacitor network.

3. The frequency generator of claim 2, wherein the resistor network comprises a plurality of resistors connected in series.

4. The frequency generator of claim 3, wherein the resistor network further comprises a plurality of resistor switches connected in parallel with a respective resistor of the plurality of resistors.

5. The frequency generator of claim 4, wherein the frequency testing circuit is configured to toggle the resistor switches to selectively vary the resistance of the resistor network when the first frequency is outside the range of the expected frequency.

6. An electronic oscillator, comprising:

a comparator connected to a first node and a third node;

a resistor network disposed between the first node and the third node;

an inverter connected to the first node and a second node;

a plurality of capacitors respectively comprising a first plate and a second plate connected to the third node;

a plurality of logic gates respectively comprising a first input connected to the second node, a second input, and an output connected to the first plate of one of the plurality of capacitors; and

a memory unit connected to the second input of the plurality of logic gates, wherein the memory unit is configured to output a separate signal to the second input of the plurality of logic gates, wherein the separate signal determines whether the first plate of one of the plurality of capacitors is connected to the second node or a non-varying voltage.

7. The electronic oscillator of claim 6, wherein the plurality of capacitors comprise:

a first group of capacitors, wherein the first plate of each capacitor of the first group of capacitors is connected to the second node; and

a second group of capacitors comprising at least one of the plurality of capacitors, wherein the first plate of each capacitor of the second group of capacitors is connected to the non-varying voltage.

8. The electronic oscillator of claim 7, wherein the resistor network comprises a plurality of resistors connected in series.

9. The electronic oscillator of claim 8, further comprising:

a plurality of resistor switches, wherein the resistor switches are connected in parallel with a respective resistor of the plurality of resistors, wherein some of the resistor switches are connected to the first node.

10. The electronic oscillator of claim 7, wherein the memory unit provides a first signal to each of the plurality of logic gates coupled to the second group of capacitors.

11. The electronic oscillator of claim 7, wherein the memory unit is configured to output a first set of signals for a first period of time and output a second set of signals for a second period of time, wherein the first set of signals is different than the second set of signals.

12. The electronic oscillator of claim 11, further comprising:

a level shifter connected to the first node, wherein the level shifter is configured to receive an input signal from the comparator, shift a voltage of the input signal, and output the voltage shifted input signal to an output node of the electronic oscillator.

13. The electronic oscillator of claim 12, wherein the memory unit is read only memory (ROM).

14. The electronic oscillator of claim 6, wherein the memory unit is configured to selectively change a voltage potential at the first plate of the plurality of capacitors between the non-varying voltage and a voltage potential at the second node.

15. A method for tuning the output frequency of an electronic oscillator, comprising:

determining whether a first frequency of an electronic oscillator is within a range of an expected output frequency, wherein the electronic oscillator comprises a comparator connected to a RC network circuit comprising a capacitor network and a resistor network;

upon determining the first frequency is not within the range of the expected output frequency, adjusting the first frequency of the electronic oscillator by selectively tuning a capacitance ratio of a first number of a plurality of capacitors within the capacitor network and a second number of the plurality of capacitors, wherein the first number of the plurality of capacitors respectively have a first plate connected to an output of an inverter coupled to the comparator, and wherein a second number of the plurality of capacitors respectively have a first plate connected to a non-varying voltage;

after selectively tuning the capacitance ratio, determining whether a second frequency is within the range of the expected output frequency; and

upon determining the second frequency is within the range of the expected output frequency, fixing the capacitance ratio between the first number of the plurality of capacitors and the second number of the plurality of capacitors.

16. The method of claim 15, wherein selectively tuning the capacitance ratio between the first number of the plurality of capacitors and the second number of the plurality of capacitors comprises:

providing separate signals to separate ones of a plurality of logic gates, wherein the outputs of the plurality of logic gates are respectively connected to the first plate of a plurality of capacitors, and inputs of the plurality of logic gates are respectively connected to the output of the inverter.

17. The method of claim 15, wherein selectively tuning the capacitance ratio between the first number of the plurality of capacitors and the second number of the plurality of capacitors comprises:

toggling a switch connected to the first plate of the plurality of capacitors, wherein the switch is toggled between the non-varying voltage and the output of the inverter.

18. The method of claim 16,

calculating a first offset frequency based on a difference between the first frequency and the expected output frequency of the electronic oscillator;

and

wherein a frequency testing circuit determines the first frequency and the first offset frequency, wherein the frequency testing circuit selectively provides a string of bits to a memory unit based on the first frequency and the first offset frequency, wherein the memory unit provides a set of signals to the electronic oscillator based on the string of bits received from the frequency testing circuit.

19. The method of claim 18, wherein fixing the capacitance ratio between the first number of the plurality of capacitors and second number of the plurality of capacitors comprises the frequency testing circuit writing the string of bits to the memory unit.

20. The method of claim 19, further comprising:

upon determining the first frequency is not within the range of the expected output frequency, based on the first offset frequency, selectively tuning a resistance of the electronic oscillator; and

upon determining the second frequency is within the range of the expected output frequency, fixing the resistance of the electronic oscillator.