COMPUTING DEVICE EXECUTING PROGRAM PERFORMING METHOD OF ANALYZING POWER NOISE IN SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE DESIGN METHOD, AND PROGRAM STORAGE MEDIUM STORING PROGRAM

• US 20180224497A1
• Filed: 04/10/2018
• Published: 08/09/2018
• Est. Priority Date: 12/05/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHEON, YOUNG HOE, HWANG, CHAN SEOK
• Granted Patent: US 10,444,276 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2646 for measuring noise G01R31/2616, G01R31/2626 take precedence
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Abstract

A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Claims

1. A method of generating a semiconductor device design in a computing device, the method comprising:

designing a power network for a semiconductor device and a plurality of cells connected to the power network to obtain a generated semiconductor device design;

analyzing power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model,

generating a generated semiconductor device design as a result of analyzing the power noise of the power network based on first modified current information and second modified current information, wherein the first modified current information is generated at a first time as a result of a first analysis based on an assumption that the power network model exists, and the second modified current information is generated at a second time after the first time by modifying present current information based on an ideal supply voltage condition using the result of the first analysis; and

storing at least part of the generated semiconductor device design in a memory associated with the computing device.

2. The method of claim 1, further comprising:

providing the semiconductor device design based on the designing of the power network for the semiconductor device and the plurality of cells connected to the power network; and

modifying the semiconductor device design based on the analyzing of the power noise of the power network.

3. The method of claim 1, wherein the analyzing of the power noise comprises:

generating the result of the first analysis at the first time by performing an arithmetic operation on a power network matrix;

generating a result of a second analysis at the second time, wherein the result of the second analysis is the second modified current information generated by modifying the present current information based on the ideal supply voltage condition using the result of the first analysis; and

generating the result of the analyzing the power noise of the power network by performing an arithmetic operation on the result of the second analysis and the power network matrix.

4. The method of claim 3, wherein the analyzing of the power noise comprises generating the power network matrix based on power network information.

5. The method of claim 3, wherein the second modified current information is generated by performing an arithmetic operation on the present current information, the result of the first analysis, and parameters of the transistor model.

6. The method of claim 5, wherein an equation calculating the second modified current information is derived from a rate between the second modified current information and the present current information when the transistor model is in a saturation region.

7. The method of claim 5, wherein the result of the first analysis and the result of the analyzing the power noise are voltage vectors of nodes connected to the transistor model and the power network model.

8. The method of claim 5, the result of the first analysis is a result of reflecting power noise when the power network model is connected to the transistor model.

9. The method of claim 3, wherein the result of the analyzing the power noise is calculated using a linear analysis.

10. The method of claim 1,

wherein the computing device comprises a memory that stores a program for generating a semiconductor device design, and a processor that executes the program to perform the method of claim 1.

11. A method of generating a semiconductor device design in a computing device, the method comprising:

designing a power network for a semiconductor device and a plurality of cells connected to the power network to obtain a generated semiconductor device design;

analyzing power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model;

generating a generated semiconductor device design as a result of analyzing power noise of the power network to generate a result of analyzing the power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model and based on first modified current information and second modified current information, wherein the first modified current information is generated at a first time as a result of a first analysis by modifying first present current information based on an ideal supply voltage condition using the result of a previous analysis of the power noise of the power network, and the second modified current information is generated at a second time after the first time as a result of a second analysis by modifying second present current information based on an ideal supply voltage condition using the result of the first analysis; and

storing at least part of the generated semiconductor device design in a memory associated with the computing device.

12. The method of claim 11, further comprising:

providing the semiconductor device design based on the designing of the power network for the semiconductor device and the plurality of cells connected to the power network; and

modifying the semiconductor device design based on the analyzing of the power noise of the power network.

13. The method of claim 12, wherein the analyzing of the power noise further comprises:

generating the result of the first analysis at the first time by performing an arithmetic operation on the first present current information and a power network matrix;

generating the result of a second analysis at the second time; and

generating the result of the analyzing the power noise of the power network by performing an arithmetic operation on the result of the second analysis and the power network matrix.

14. The method of claim 13, wherein the analyzing of the power noise comprises generating the power network matrix based on power network information.

15. The method of claim 13, wherein the second modified current information is generated by performing an arithmetic operation on the second present current information, the result of the first analysis, and parameters of the transistor model.

16. The method of claim 15, wherein an equation calculating the second modified current information is derived from a rate between the second modified current information and the second present current information when the transistor model is in a saturation region.

17. The method of claim 15, wherein the result of the first analysis and the result of the analyzing the power noise are voltage vectors of nodes connected to the transistor model and the power network model.

18. The method of claim 15, the result of the first analysis is a result of reflecting power noise when the power network model is connected to the transistor model.

19. The method of claim 13, wherein the result of the analyzing the power noise is calculated using a linear analysis.

20. A method of generating a semiconductor device design in a computing device, the method comprising:

designing a power network for a semiconductor device and a plurality of cells connected to the power network to obtain a generated semiconductor device design;

analyzing power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model;

generating a generated semiconductor device design as a result of analyzing power noise of the power network to generate a result of analyzing the power noise of the power network based on modeling the semiconductor device as a power network model and a transistor model and based on first modified current information, second modified current information and third modified current information, wherein the first modified current information is generated at a first time as a result of a first analysis by modifying first present current information based on an assumption that the power network model exists, the second modified current information is generated at a second time after the first time as a result of a second analysis by modifying second present current information based on an ideal supply voltage condition using the result of the first analysis of the power noise of the power network, and the third modified current information is generated at a third time after the second time as a result of a third analysis by modifying third present current information based on an ideal supply voltage condition using the result of the second analysis; and

storing at least part of the generated semiconductor device design in a memory associated with the computing device.