REFERENCE GENERATOR AND CURRENT SOURCE TRANSISTOR BASED ON COMPLEMENTARY CURRENT FIELD-EFFECT TRANSISTOR DEVICES

• US 20180224878A1
• Filed: 07/29/2016
• Published: 08/09/2018
• Est. Priority Date: 07/30/2015
• Status: Active Grant

• Current Assignee: Circuit Seed, LLC
• Original Assignee: Circuit Seed, LLC
• Inventors: SCHOBER, Susan Marya, SCHOBER, Robert C.
• Granted Patent: US 10,514,716 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 3/245 producing a voltage or current as a predetermined function of the temperature
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03F 3/165 with junction-FET's

Abstract

Existing proportional to absolute temperature (PTAT)/complementary-to-absolute-temperature (CTAT) reference voltage circuit requires a large components count and foot print, precise device matching for accuracy and unsatisfactory sensitivity error or variation to temperature and humidity. The present invention relates to a novel approach for such reference voltage circuit based on a self-biased complementary pair of n-type and p-type current field-effect transistors, which provides rail PTAT, rail CTAT and analog reference voltages.

Claims

1. A proportional to absolute temperature reference voltage circuit, comprising:

a complementary pair of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET), each of said NiFETs and PiFETs comprises;

a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source channel and said drain channel;

wherein said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form a common gate terminal, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and drain terminals of said NiFET and said PiFET are connected together to form an output; and

wherein said common gate of said complimentary pair is connected together with said output of said complementary pair for generating a analog zero reference voltage, providing a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion terminal of said PiFET and a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion terminal of said NiFET.

2. A positive and negative current references generator, comprising

a. first and second complementary pairs of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET), each of said NiFETs and PiFETs comprises:

a diffusion terminal of a corresponding conductivity type of said each of said PiFETs and NiFETs, a source terminal, a drain terminal and a gate terminal,

said drain terminal defines a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal capacitively coupled to said source channel and said drain channel;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form a common gate terminal, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output;

wherein said common gates of said first and second complementary pairs are connected together with said output of said first complementary pair, providing a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion terminal of said PiFET of said first complementary pair to said diffusion terminal of said PiFET of said second complementary pair for generating said negative reference current; and

providing a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion terminal of said NiFET of said first complementary pair to said diffusion channel of said NiFET of said second complementary pair for generating said positive reference current.

3. A stacked proportional to absolute temperature reference voltage circuit, comprising:

a plurality of complementary pairs of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET), each of said NiFETs and PiFETs comprises;

a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal capacitively coupled to said source channel and said drain channel;

wherein said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form a common gate terminal, and drain terminals of said NiFET and said PiFET are connected together to form an output; and

wherein said common gate of said complimentary pair is connected together with said output of said complementary pair for generating a analog zero reference voltage, providing a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion terminal of said PiFET and a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion terminal of said NiFET

wherein said source terminal of said NiFET of a first one of said plurality of said complementary pairs is connected to negative power supply and said source terminal of said PiFET of said first one of said plurality of said complementary pairs is connected to positive power supply,

said source terminal of said NiFET of a subsequent one of said plurality of said complementary pairs receives PTAT reference voltage output of a previous one of said plurality of said complementary pairs;

said source terminal of said PiFET of said subsequent one of said plurality of said complementary pairs receives CTAT reference voltage output of said previous one of said plurality of said complementary pairs; and

said common gate of said subsequent one of said plurality of said complementary pairs receives said output of said previous one of said plurality of said complementary pairs.

4. A proportional-to-absolute temperature reference voltages and complementary-to-absolute temperature reference voltages generator circuit, comprising:

a. a first complementary pair of a n-type current field-effect transistor (NiFET) and a p-type current field-effect transistor (PiFET),

b. a second complementary pair of NiFET and PiFET;

each of said NiFETs and PiFETs comprises;

i. a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of a corresponding conductivity type of said each of said PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source channel and said drain channel;

wherein said drain terminals of said NiFET and said PiFET of said first complementary pair are coupled together;

said drain terminals of said NiFET and said PiFET of said second complementary pair are coupled together;

said source terminal of said PiFET of said first complementary pair receives a positive power supply;

said source terminal of said NiFET of said second complementary pair receives a negative power supply;

wherein said gate terminals of said PiFETs of said first and said second complementary pairs and said gate terminals of said NiFETs of said first and second complementary pairs are connected together to form a common gate and to receive said source terminal of said NiFET of said first complementary pair and said source terminal of said PiFET of said second complementary pair for generating a positive rail complementary-to-absolute-temperature (or CTAT) reference voltage output at said diffusion terminal of said PiFET of said first complementary pair, CTAT analog ground reference voltage output at said diffusion terminal of said NiFET of said first complementary pair, an analog ground reference voltage at said common gate, a negative rail proportional-to-absolute-temperature (or PTAT) reference voltage output at said diffusion terminal of said NiFET of said second complementary pair.