INTEGRATION OF VERTICAL FIELD-EFFECT TRANSISTORS AND SADDLE FIN-TYPE FIELD EFFECT TRANSISTORS

• US 20180226402A1
• Filed: 02/08/2017
• Published: 08/09/2018
• Est. Priority Date: 02/08/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Sung, Min Gyu, Lim, Kwan-Yong
• Granted Patent: US 10,163,900 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

Claims

1. A structure fabricated using a substrate, the structure comprising:

trench isolation in the substrate that defines a first device region and a second device region;

a saddle fin-type field-effect transistor including a first semiconductor fin projecting from the first device region and a first gate electrode, the first semiconductor fin having a top surface and a channel recess extending from the top surface into the first semiconductor fin, and the first gate electrode positioned within the channel recess and on the trench isolation; and

a vertical field-effect transistor including a second semiconductor fin projecting from the second device region and a second gate electrode associated with the second semiconductor fin,

wherein the trench isolation has a top surface, and the top surface of the trench isolation adjacent to the first semiconductor fin in the first device region is recessed relative to the top surface of the trench isolation adjacent to the second semiconductor fin in the second device region.

2. The structure of claim 1 wherein the vertical field-effect transistor includes a first source/drain region and a second source/drain region, and the second gate electrode is arranged in a vertical direction relative to the top surface of the trench isolation between the first source/drain region and the second source/drain region.

3. The structure of claim 2 wherein the vertical field-effect transistor includes a spacer layer between the second gate electrode and the first source/drain region, and the first device region is free of the spacer layer.

4. The structure of claim 1 wherein the vertical field-effect transistor includes a spacer layer on the second device region adjacent to the first semiconductor fin, and the top surface of the trench isolation in the first device region is free of the spacer layer.

5. The structure of claim 4 wherein the first semiconductor fin includes a sidewall, and the first gate electrode of the saddle fin-type field-effect transistor extends from the channel recess along the sidewall of the first semiconductor fin to the top surface of the trench isolation.

6. The structure of claim 1 wherein the first semiconductor fin and the second semiconductor fin have equal widths.

7. The structure of claim 1 wherein the first gate electrode of the saddle fin-type field-effect transistor positioned on the trench isolation has a first height, the second gate electrode of the vertical field-effect transistor has a second height, and the first height is greater than the second height.

8. A method comprising:

forming trench isolation in a substrate that defines a first device region and a second device region;

forming a first semiconductor fin projecting from the first device region and a second semiconductor fin projecting from the second device region;

forming a vertical field-effect transistor using the first semiconductor fin;

forming a saddle fin-type field-effect transistor using the second semiconductor fin; and

recessing a top surface of the trench isolation in the second device region adjacent to the second semiconductor fin relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

9. The method of claim 8 wherein the first semiconductor fin and the second semiconductor fin have equal widths.

10. The method of claim 8 further comprising:

forming a channel recess that extends from a top surface of the first semiconductor fin into the first semiconductor fin;

forming a first gate electrode of the saddle fin-type field-effect transistor within the channel recess and on the trench isolation adjacent to the second semiconductor fin; and

forming a second gate electrode of the vertical field-effect transistor adjacent to the first semiconductor fin.

11. The method of claim 10 wherein the first gate electrode of the saddle fin-type field-effect transistor positioned on the trench isolation has a first height, the second gate electrode of the vertical field-effect transistor has a second height, and the first height is greater than the second height.

12. The method of claim 10 wherein the second gate electrode of the vertical field-effect transistor is concurrently formed with the first gate electrode of the saddle fin-type field-effect transistor.

13. The method of claim 10 further comprising:

forming a spacer layer on the first device region adjacent to the first semiconductor fin and on the second device region adjacent to the second semiconductor fin; and

removing the spacer layer from the second device region, wherein the spacer layer on the first device region is masked when the spacer layer is removed from the second device region.

14. The method of claim 13 wherein the second gate electrode of the vertical field-effect transistor is formed on the spacer layer adjacent to the first semiconductor fin.

15. The method of claim 13 wherein the second gate electrode of the vertical field-effect transistor is formed after the spacer layer is removed from the second device region adjacent to the second semiconductor fin.

16. The method of claim 13 wherein the top surface of the trench isolation in the second device region adjacent to the first semiconductor fin is recessed after the spacer layer is removed from the substrate from the first device region adjacent to the first semiconductor fin.

17. The method of claim 16 wherein the spacer layer masks the top surface of the first device region when the top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed.

18. The method of claim 13 wherein the top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed with an etching process that removes a first material of the dielectric layer selective to a second material of the spacer layer.

19. The method of claim 8 wherein the top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed with an etching process that removes a first material of the dielectric layer selective to a second material of the second semiconductor fin.

20. The method of claim 8 wherein the first semiconductor fin and the second semiconductor fin are concurrently formed, and the first semiconductor fin and the second semiconductor fin have equal widths.