Three-Dimensional Vertical One-Time-Programmable Memory Comprising Schottky Diodes

• US 20180226414A1
• Filed: 04/08/2018
• Published: 08/09/2018
• Est. Priority Date: 04/16/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: ZHANG, Guobiao
• Granted Patent: US 10,559,574 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/0045 Read using current through the cell
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

The present invention discloses a three-dimensional vertical read-only memory (3D-OTP_V) comprising Schottky diodes. It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. A plurality of Schottky diodes are formed between the horizontal address lines and the vertical address lines.

Claims

1. A three-dimensional vertical read-only memory (3D-OTP_V), comprising:

a semiconductor substrate comprising a substrate circuit;

a plurality of vertically stacked horizontal address lines above said semiconductor circuit;

a plurality of memory holes through said horizontal address lines;

an antifuse layer formed on the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;

a plurality of vertical address line in said memory holes;

a plurality of OTP cells at the intersections of said horizontal address lines and said vertical address lines;

wherein a plurality of Schottky diodes are formed between said horizontal address lines and said vertical address lines.

2. The 3D-OTP_V according to claim 1, wherein said horizontal address lines comprise at least a metallic material, said vertical address lines comprise at least a doped semiconductor material.

3. The 3D-OTP_V according to claim 1, wherein said horizontal address lines comprise at least a doped semiconductor material, said vertical address lines comprise at least a metallic material.

4. The 3D-OTP_V according to claim 1, wherein each of said OTP cells further comprises a quasi-conductive layer.

5. The 3D-OTP_V according to claim 2, wherein the resistance of said quasi-conductive layer at the read voltage is substantially lower than when the applied voltage has a magnitude smaller than or polarity opposite to that of the read voltage.

6. The 3D-OTP_V according to claim 1, wherein all OTP cells coupled to selected one of said horizontal address lines are read out in a single read cycle.

7. The 3D-OTP_V according to claim 1, wherein said plurality of OTP cells form a vertical OTP string.

8. The 3D-OTP_V according to claim 7, further comprising a vertical transistor coupled to said OTP string.

9. The 3D-OTP_V according to claim 8, wherein said vertical transistor is formed in a first portion of selected one of said memory holes, and said OTP string is formed in a second portion of said selected one of said memory holes.

10. The 3D-OTP_V according to claim 1, wherein said OTP cells have more than two states, the OTP cells in different states having different resistance value.

11. A three-dimensional vertical read-only memory (3D-OTP_V), comprising:

a semiconductor substrate comprising a substrate circuit;

a plurality of vertically stacked horizontal address lines above said semiconductor circuit, said horizontal address lines comprising at least a metallic material;

a plurality of memory holes through said horizontal address lines;

an antifuse layer formed on the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;

a plurality of vertical address line in said memory holes, said vertical address lines comprising at least a doped semiconductor material;

a plurality of OTP cells at the intersections of said horizontal address lines and said vertical address lines.

12. The 3D-OTP_V according to claim 11, wherein each of said OTP cells further comprises a quasi-conductive layer.

13. The 3D-OTP_V according to claim 11, wherein all OTP cells coupled to selected one of said horizontal address lines are read out in a single read cycle.

14. The 3D-OTP_V according to claim 11, wherein a vertical transistor is formed in a first portion of selected one of said memory holes, and said plurality of OTP cells are formed in a second portion of said selected one of said memory holes.

15. The 3D-OTP_V according to claim 11, wherein said OTP cells have more than two states, the OTP cells in different states having different resistance value.

16. A three-dimensional vertical read-only memory (3D-OTP_V), comprising:

a semiconductor substrate comprising a substrate circuit;

a plurality of vertically stacked horizontal address lines above said semiconductor circuit, said horizontal address lines comprising at least a doped semiconductor material;

a plurality of memory holes through said horizontal address lines;

an antifuse layer formed on the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;

a plurality of vertical address line in said memory holes, said vertical address lines comprising at least a metallic material;

a plurality of OTP cells at the intersections of said horizontal address lines and said vertical address lines.

17. The 3D-OTP_V according to claim 16, wherein each of said OTP cells further comprises a quasi-conductive layer.

18. The 3D-OTP_V according to claim 16, wherein all OTP cells coupled to selected one of said horizontal address lines are read out in a single read cycle.

19. The 3D-OTP_V according to claim 16, wherein a vertical transistor is formed in a first portion of selected one of said memory holes, and said plurality of OTP cells are formed in a second portion of said selected one of said memory holes.

20. The 3D-OTP_V according to claim 16, wherein said OTP cells have more than two states, the OTP cells in different states having different resistance value.