SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20180226473A1
• Filed: 04/02/2018
• Published: 08/09/2018
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KOBAYASHI, Kenya, MATSUDA, Tetsuo, HIMORI, Yosuke, NISHIGUCHI, Toshifumi
• Granted Patent: US 11,011,609 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of the first conductivity type provided on the second semiconductor region, a first insulating part provided in the first semiconductor region, a first electrode provided in the first semiconductor region, the first insulating part disposed between the first electrode and the first semiconductor region, a second insulating part provided on the first electrode, a gate electrode provided on the second insulating part, a gate insulating part provided between the gate electrode and the second semiconductor region, and a second electrode provided on the second semiconductor region and on the third semiconductor region, and is electrically connected to the second semiconductor region, the third semiconductor region, and the first electrode.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate including;

a first semiconductor layer having an upper surface in which a trench is formed;

a first insulating layer that is provided along an inner wall of the trench;

a first electrode that is provided in a lower portion in the trench on the first insulating layer; and

a second insulating layer that is provided on an upper surface of the first electrode;

forming a third insulating layer along a surface of the first insulating layer and along a surface of the second insulating layer, the third insulating layer having an etching rate lower than an etching rate of the first insulating layer for an etching process;

forming a fourth insulating layer on the third insulating layer, the fourth insulating layer having an etching rate higher than an etching rate of the third insulating layer for the etching process;

removing at least a portion of the first insulating layer, a portion of the third insulating layer, and a portion of the fourth insulating layer;

forming a first projection and a second projection in an upper surface of the third insulating layer, positioned on the second insulating layer and protruding upward; and

forming a gate electrode on the second insulating layer and the third insulating layer.

2. The method of claim 1, wherein removing at least the portion of the first insulating layer, the portion of the third insulating layer, and the portion of the fourth insulating layer is performed using the etching process, such that the fourth insulating layer is etched more than the third insulating layer.

3. The method of claim 2, wherein the etching process is performed at least until the fourth insulating layer is removed.

4. The method of claim 1, wherein the third insulating layer is formed to include boron in a greater concentration than a boron concentration of at least one of the first insulating layer and the second insulating layer.

5. The method of claim 4, wherein the fourth insulating layer is formed to include boron in greater concentration than the boron concentration of the third insulating layer.

6. The method of claim 1, wherein the third insulating layer is formed such that the trench is not completely filled.

7. The method of claim 6, wherein the third insulating layer is formed such that the third insulating layer defines a recess, and the fourth insulating layer is disposed on the third insulating layer and in the recess.

8. The method of claim 1, wherein the second insulating layer is thinner than the first insulating layer.

9. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor layer having an upper surface;

forming a trench in the upper surface of the first semiconductor layer;

forming a first insulating layer along an inner wall of the trench;

forming a first electrode on the first insulating layer;

forming a second insulating layer on an upper surface of the first electrode;

forming a third insulating layer along a surface of the first insulating layer and along a surface of the second insulating layer;

forming a fourth insulating layer on the third insulating layer;

removing at least a portion of the first insulating layer, a portion of the third insulating layer, and a portion of the fourth insulating layer to form a first projection and a second projection in an upper surface of the third insulating layer, positioned on the second insulating layer and protruding upward; and

forming a gate electrode on the second insulating layer and the third insulating layer.

10. The method of claim 9, wherein forming the first insulating layer comprises thermally oxidizing the first semiconductor layer.

11. The method of claim 9, wherein forming the first electrode comprises forming a conductive layer on the first insulating layer, and etching the conductive layer to form the first electrode in a lower portion of the trench.

12. The method of claim 9, further comprising disposing a second semiconductor layer on the first semiconductor layer, and disposing a third semiconductor layer on the second semiconductor layer prior to forming the trench.

13. The method of claim 12, wherein the trench is further formed in the second semiconductor layer and the third semiconductor layer.

14. The method of claim 9, wherein the third insulating layer is formed to include boron in a greater concentration than a boron concentration of at least one of the first insulating layer and the second insulating layer.

15. The method of claim 9, wherein the third insulating layer is formed to define a recess.

16. The method of claim 15, wherein the fourth insulating layer is formed in the recess and on the third insulating layer.