MULTI-STAGE AND FEED FORWARD COMPENSATED COMPLEMENTARY CURRENT FIELD EFFECT TRANSISTOR AMPLIFIERS

• US 20180226930A1
• Filed: 07/29/2016
• Published: 08/09/2018
• Est. Priority Date: 07/30/2015
• Status: Active Grant

• Current Assignee: Circuit Seed, LLC
• Original Assignee: Circuit Seed, LLC
• Inventors: SCHOBER, Susan Marya, SCHOBER, Robert C.
• Granted Patent: US 10,491,177 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H03F 1/083 in transistor amplifiers H03F1/10 - H03F1/22 take precedence
• CPC Class Codes: H03F 2203/45246 the dif amp being biased in the subthreshold region
• CPC Class Codes: H03F 2203/45692 the LC comprising one or more resistors in series with a capacitor coupled to the LC by feedback
• CPC Class Codes: H03F 3/3022 CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits

Abstract

The present invention relates to a multi-stage and feed forward compensated complimentary current field effect transistor amplifiers, enabling a charge-based approach that takes advantage of the exponential properties incurred in sub-threshold operation. A plurality of complimentary pairs of novel current field effect transistors are connected in series to form a multi-stage amplifier.

Claims

1. A voltage amplifier, comprising:

at least three complementary pairs of current field effect transistors, each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET),

each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for each of at least three complementary pairs, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of NiFET is connected to a negative power supply and said source terminal of said PiFET is connected to a positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs.

2. The voltage amplifier as recited in claim 1 further comprises a pair of roll-off capacitors, capacitively connecting output of said second pair to said diffusion terminals of said first pair of said NiFET and PiFET.

3. The voltage amplifier as recited in claim 1 or 2 further comprises an additional pair of an NiFET and PiFET as a feed forward pair, wherein said feed forward pair receives input of said voltage amplifier as an input to gate terminals of said feed forward pair, and couples said output of said third pair with drain terminals of said NiFET and PiFET of said feed forward pair to form a feed forward output.

4. A differential voltage amplifier, comprising:

a. positive and negative voltage input terminals for receiving differential voltage input;

b. positive and negative voltage output terminals for outputting differential voltage output;

c. an analog ground reference terminal for receiving analog ground reference;

d. first and second multistage amplifiers, each of said first and second multistage amplifiers comprising;

i. at least three complementary pairs of current field effect transistors, each complementary pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET),

for each complementary pair, each of said PiFET and said NiFET has a source terminal, a drain terminal, a gate terminal and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

said gate terminal of said PiFET and a gate terminal of said NiFET are connected together to form an input, said source terminal of NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs,

wherein, for each of said first and second multistage amplifiers, said input of said first complementary pair forms an input terminal and said output of said last pair forms an output terminal;

e. first and second capacitors, each of said first and second capacitors has a first and second terminals, said second terminal of said first capacitor is connected to said input terminal of said first multistage amplifier, and said second terminal of said second capacitor is connected to said input terminal of said second multistage amplifier;

f. a plurality of switches controlled by a control signal, wherein control signal alternates phases comprising a setup phase and enable phase;

wherein during said setup phase of said control signal, said plurality of switches cause said first terminals of said first and second capacitors to connect to said analog ground reference terminal and said output terminal to connect to said input terminal of each of said first and second multistage amplifiers while disconnecting said positive and negative voltage input terminals and positive and negative voltage output terminals; and

during said enable phase of said control signal, said plurality of switches cause said negative voltage input terminal to connect to said first terminal of said first capacitor and said positive voltage input terminal to said first terminal of said second capacitor, and to connect said output terminal of said first multistage amplifier to said positive voltage output terminal and said output terminal of said second multistage amplifier to said negative voltage output terminal.

5. A continuous differential voltage amplifier, comprising:

a. positive and negative voltage input terminals for receiving differential voltage input;

b. positive and negative voltage output terminals for outputting differential voltage output;

c. an analog ground reference terminal for receiving analog ground reference;

d. first and second differential voltage amplifiers as recited in claim 4, wherein said first differential voltage amplifier is operable with a first control signal and said second differential voltage amplifier is operable with a second control signal, wherein said first and second control signals alternates setup and enable phases;

wherein said positive voltage input terminals of said first and second differential voltage amplifiers are connected to said positive voltage input terminal of said continuous differential voltage amplifier, said negative voltage input terminals of said first and second differential voltage amplifiers are connected to said negative voltage input terminal of said continuous differential voltage amplifier, positive output terminals of said first and second differential voltage amplifiers are connected to said positive voltage output terminal of said continuous differential voltage amplifier, and said negative voltage output terminals of said first and second differential voltage amplifiers are connected to said negative voltage output terminal of said continuous differential voltage amplifier;

wherein said first and second control signals are out of phase whereby continuous output is provided from said positive and negative voltage terminals of said continuous differential voltage amplifier.

6. The continuous differential voltage amplifier as recited in claim 5, wherein a phase difference between said first control signal and said second control signal is 180 degrees.

7. A differential voltage amplifier, comprising:

a. positive and negative voltage input terminals for receiving differential voltage input;

b. positive and negative voltage output terminals for outputting differential voltage output;

c. an analog ground reference terminal for receiving analog ground reference;

d. first and second multistage amplifiers, each of said first and second multistage amplifiers comprising;

i. at least three complementary pairs of current field effect transistors,

a) each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET),

a. each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs,

wherein, for each of first and second multistage amplifiers, said input of said first complementary pair forms an input terminal and said output of said last complementary pair forms an output terminal;

e. first and second capacitors, each of said first and second capacitors has a first terminal and second terminal, said second terminal of said first capacitor is connected to said input terminal of said first multistage amplifier, and said second terminal of said second capacitor is connected to said input terminal of said second multistage amplifier;

f. third and fourth capacitors, each of said second and third capacitors has a first terminal and second terminal;

g. a plurality of switches controlled by a control signal, wherein control signal alternates phases comprising a setup phase and enable phase;

wherein during said setup phase of said control signal, said plurality of switches cause said first terminals of said first and second capacitors to connect to said analog ground reference terminal, said output terminal to connect to said input terminal of each of said first and second multistage amplifiers, said first terminal of said third capacitor and said second terminal of said fourth capacitor to connect to said positive voltage input terminal, and said second terminal of said third capacitor and said first terminal of said fourth capacitor to connect to said negative voltage input terminal while disconnecting said positive and negative voltage output terminals; and

during said enable phase of said control signal, said plurality of switches causes said output terminal of said first multistage amplifier to capacitively connect to said input terminal of said first multistage amplifier by connecting said third and first capacitors in series, said output terminal of said second multistage amplifier to capacitively connect to said input terminal of said second multistage amplifier by connecting said fourth and second capacitors in series, and said output terminal of said first multistage amplifier to connect to said positive voltage output terminal and said output terminal of said second multistage amplifier to connect to said negative voltage output terminal, while disconnecting said negative and positive voltage input terminals and analog ground reference terminal.

8. A sample and hold voltage amplifier, comprising:

a. positive and negative voltage input terminals for receiving differential voltage input;

b. an output terminal for outputting voltage output;

c. a multistage amplifier comprising;

i. at least three complementary pairs of current field effect transistors,

each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET),

each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output,

wherein said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs,

wherein, for each of said first and second multistage amplifier, said input of said first pair forms an inputer terminal, and said output of said last pair forms an output terminal;

d. a plurality of switches control by a control signal, wherein said control signal alternates between first and second phases;

e. a capacitor having a first terminal and second terminal, said second terminal of said capacitor is connected to said input terminal of said multistage amplifier;

wherein said setup phase of said control signal causes said plurality of switches to connect said positive voltage input terminal to said first terminal of said capacitor, and further causes said multistage amplifier to be self-biased by connecting said output terminal to said input terminal of said multistage amplifier, and

wherein said enable phase of said control signal causes said plurality of switches to connect said negative voltage input terminal to said first terminal of said capacitor, and further causing said output terminal of said multistage amplifier to said output voltage terminal.

9. The amplifier as recited in claim 8 further comprises a reference terminal for receiving a reference for said voltage output terminal to resistively and/or capacitively couple said reference terminal with said voltage output terminal.

10. A sample and hold voltage amplifier, comprising:

a. positive and negative voltage input terminals for receiving differential voltage input;

b. an output terminal for outputting voltage output;

c. a reference terminal for receiving output voltage reference;

d. a multistage amplifier comprising;

i. at least three complementary pairs of current field effect transistors, each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs,

wherein, for each multistage amplifier, said input of said first complementary pair forms an inputer terminal, and said output of said last complementary pair forms an output terminal;

e. first and second capacitors, each of said first and second capacitors has a first and second terminal, said second terminal of said first capacitor is connected to said input terminal of said first multistage amplifier;

f. a plurality of switches controlled by a control signal, wherein control signal alternates a setup phase and enable phase repeatedly;

wherein said output terminal of said multistage amplifier is connected to said output terminal of said sample and hold voltage amplifier;

wherein said setup phase of said control signal causes said plurality of switches to connect said positive voltage input terminal to said first terminal of said second capacitor, said negative voltage input terminal to said second terminal of said second capacitor, said multistage amplifier to be self-biased by connecting said output terminal of said multistage amplifier to said input terminal of said multistage amplifier, and said reference terminal to said first terminal of said first capacitor;

wherein said enable phase of said control signal causes said first terminal of said second capacitor to couple with said output terminal of said multistage amplifier, said second terminal of said second capacitor to connect to said first terminal of said first capacitor.

11. The sample and hold voltage amplifier as recited in claim 10, wherein during transition from said setup phase to said enable phase of said control signal, a corresponding of said plurality of switches that causes said multistage amplifier to be self-bias and to connect said reference to said first terminal of said first capacitor during said setup phase to be disconnected earlier than another corresponding portion of said plurality of switches that causes to connect said positive voltage input terminal to said first terminal of said second capacitor and said negative voltage input terminal to said second terminal of said second capacitor.

12. A precise twice gain analog amplifier, comprising:

a. positive and negative voltage input terminals for receiving differential voltage input;

b. an output terminal for outputting voltage output;

c. an output reference;

d. a multistage amplifier comprising;

i. at least three complementary pairs of current field effect transistors, each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output; and

wherein said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs;

wherein said input of said first complementary pair forms an input terminal, and said output of said last complementary pair forms an output terminal;

e. a plurality of switches controlled by a control signal, wherein said control signal alternates first and second phases;

f. an offset capacitor having first and second terminals;

g. first and second capacitors, each having first and second terminals;

h. a plurality of switches operable by said control signal;

wherein said second terminal of said offset capacitor is connected to said input of said multistage amplifier;

wherein during said setup phase of said control signal, said plurality of switches causes;

i. the multistage amplifier to be self-biased by connecting said output terminal of said multistage amplifier to said input of said multistage amplifier;

ii. the output reference to connect to said first terminal of said offset capacitor;

iii. the first and second capacitors to be connected in parallel by connecting said first terminals of said first and second capacitors to said positive voltage input terminal and said second terminals of said first and second capacitors to said negative voltage input terminal; and

during said enable phase of said control signal, said plurality of switches causes;

i. the output terminal of said multistage amplifier to be capacitively connected to said input terminal of said multistage amplifier by connecting said output terminal of said multistage amplifier to said first terminal of said first capacitor, said second terminal of said first capacitor to said the first terminal of said second capacitor, said second terminal of said second capacitor to said first terminal of said offset capacitor.

13. A continuous amplifier, comprising:

a. positive and negative voltage input terminals for receiving differential voltage input;

b. an output terminal;

c. a plurality of switches controlled by first and second control signals, wherein each control signal alternates a setup phase and enable phase repeatedly and said first and second control signals are 180 degree differences in phase;

d. first and second multistage amplifiers, each of said first and second multistage amplifiers comprising;

i. at least three complementary pairs of current field effect transistors, each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output; and

wherein said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs;

wherein, for each multistage amplifier, said input of said first complementary pair forms an input terminal, and said output of said last complementary pair forms output terminal;

e. a first and second offset capacitor, each having first and second terminals,

wherein said second terminal of said first offset capacitor is connected to said input terminal of said first multistage amplifier, and said second terminal of said second offset capacitor is connected to said input terminal of said second multistage amplifier;

wherein said setup phase of said first control signal causes to connect said positive voltage input terminal to said first terminal of said first offset capacitor, and further causes said first multistage amplifier to be self-biased by connecting said output terminal of said first multistage amplifier to said input terminal of said first multistage amplifier;

the setup phase of said second control signal causes to connect said positive voltage input terminal to said first terminal of said second offset capacitor, and further causes said second multistage amplifier to be self-biased by connecting said output terminal of said second multistage amplifier to said input terminal of said second multistage amplifier;

the enable phase of said first control signal causes to connect said negative voltage input terminal to said first terminal of said first offset capacitor and said output terminal of said first multistage amplifier to said output terminal of said continuous amplifier; and

the enable phase of said second control signal causes to connect said negative voltage input terminal to said first terminal of said second offset capacitor and said output terminal of said second multistage amplifier to said output terminal of said continuous amplifier.

14. A sample and hold amplifier, comprising:

a. a positive and negative voltage input terminals;

b. an output terminal;

c. a plurality of references of said different levels, including an analog ground;

d. a plurality of offset capacitors corresponding to said number of references, each of said plurality of said offset capacitors includes first and second terminals;

e. a plurality of flying capacitors, each of said plurality of flying capacitors has first and second terminals;

f. a plurality of switches controlled by a clock that alternates setup and enable phases;

g. a multistage amplifier comprising;

i. at least three complementary pairs of current field effect transistors, each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein, for each multistage amplifier, said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs;

wherein, for each multistage amplifier, said input of said first complementary pair forms an input terminal, and said output of said last complementary pair forms an output terminal;

wherein said output terminal of said multistage amplifier is in communication with said output terminal of said sample and hold amplifier, and said second terminals of said plurality of said offset capacitors are connected to said input terminal of said multistage amplifier;

wherein, during setup phase of said clock, said plurality of switches causes to connect said first terminals of said plurality of flying capacitors to said positive voltage input terminal of said sample and hold amplifier, to connect said second terminals of said plurality of flying capacitors to said negative input voltage input terminal of said sample and hold amplifier, to connect each of said first terminals of said plurality of said offset capacitors to said corresponding one of said plurality of references, and to have said multistage amplifier to be self-biased by connecting said output terminal of said multistage amplifier to said input terminal of said multistate amplifier; and

during enable phase of said clock, said plurality of switches causes to connect said plurality of said flying capacitors in series with each other and with a selected one of said plurality of said offset capacitors in series, and to capacitively couple said output terminal of said multistage amplifier through said plurality of said flying capacitors and said selected one of said plurality of said offset capacitors to said input terminal of said multistage amplifier;

wherein said selected one of said plurality of said offset capacitors is connected to said corresponding one of said plurality of references with a voltage level of said corresponding one of said plurality of references is higher than or equal to said voltage level at said positive voltage input terminal of said sample and hold amplifier, and said voltage level at said positive voltage input terminal of said sample and hold amplifier is higher than a voltage level of one level lower than said corresponding one of said plurality of references.

15. A digital to analog converter, comprising:

a. a positive and negative voltage input terminals;

b. an output terminal;

c. a plurality of references of said different levels, including an analog ground;

d. a plurality of offset capacitors corresponding to said number of references, each of said plurality of said offset capacitors includes first and second terminals;

e. a plurality of flying capacitors, each of said plurality of flying capacitors has first and second terminals;

f. a plurality of switches controlled partly by a clock that alternates setup and enable phases;

g. a multistage amplifier comprising;

i. at least three complementary pairs of current field effect transistors, each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET of said each pair is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output; and

wherein, for each multistage amplifier, said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs;

wherein, for each multistage amplifier, said first complementary pair forms an input terminal and said output of said last complementary pair forms an output terminal;

wherein said output terminal of said multistage amplifier is in communication with said output terminal of said sample and hold amplifier, and said second terminals of said plurality of said offset capacitors are connected to said input terminal of said multistage amplifier;

wherein, during setup phase of said clock, said plurality of switches causes to couple said plurality of said flying capacitors with said positive and negative voltage input terminals of said sample and hold amplifier, to connect each of said first terminals of said plurality of said offset capacitors to said corresponding one of said plurality of references, and to have said multistage amplifier to be self-biased by connecting said output terminal of said multistage amplifier to said input terminal of said multistate amplifier; and

during enable phase of said clock, said plurality of switches causes to couple said plurality of said flying capacitors with a selected one of said plurality of said offset capacitors, and to capacitively couple said output terminal of said multistage amplifier through said plurality of said flying capacitors and said selected one of said plurality of said offset capacitors to said input terminal of said multistage amplifier;

wherein said selected one of said plurality of said offset capacitors is selected based on a value of a digital representation for an analog output.

16. The digital to analog converter as recited in claim 15, wherein said plurality of said flying capacitors are coupled in series during said setup phase of said clock, and said plurality of said flying capacitors are coupled in parallel during said enable phase of said clock.

17. A digital to analog converter, comprising:

a. a positive and negative voltage input terminals;

b. a positive and negative voltage output terminals;

c. a plurality of references of said different levels, including an analog ground;

d. a first plurality of offset capacitors and a second plurality of offset capacitors, a number of each of said first and second plurality of said offset capacitors corresponds to said number of said references, each of said first and second plurality of said offset capacitors includes first and second terminals;

e. a first and second flying capacitors, each of said first and second flying capacitors has first and second terminals;

f. a plurality of switches controlled partly by a clock that alternates setup and enable phases;

g. a first and second multistage amplifiers, each of said first and second multistage amplifiers comprising;

i. at least three complementary pairs of current field effect transistors, each pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of PiFET and NiFET has a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein, for each multistage amplifier, said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs,

wherein, for each multistage amplifier, said input of said first complementary pair forms an input terminal, and said output of said last complementary pair forms an output terminal;

wherein said output terminals of said first multistage amplifier is in communication with said positive voltage output terminal of said sample and hold amplifier, said output terminals of said second multistage amplifier is in communication with said negative voltage output terminal of said sample and hold amplifier, said second terminals of said first plurality of said offset capacitors are connected to said input terminal of said first multistage amplifier, and said second terminals of said second plurality of said offset capacitors are connected to said input terminal of said second multistage amplifier;

wherein, during setup phase of said clock, said plurality of switches causes to couple said first and second flying capacitors in series with said positive and negative voltage input terminals of said sample and hold amplifier, to connect each of said first terminals of said first and second plurality of said offset capacitors to said corresponding one of said plurality of references, and to have said first and second multistage amplifiers to be self-biased by connecting said output terminal of said first multistage amplifier to said input terminal of said first multistate amplifier and by connecting said output terminal of said second multistage amplifier to said input terminal of said second multistate amplifier; and

during enable phase of said clock, said plurality of switches causes to couple said first flying capacitor with a selected one of said first plurality of said offset capacitors in series, to couple said second flying capacitor with a selected one of said second plurality of said offset capacitors in series, to capacitively couple said output terminal of said first multistage amplifier through said first flying capacitor and said selected one of said first plurality of said offset capacitors to said input terminal of said first multistage amplifier, and to capacitively couple said output terminal of said second multistage amplifier through said second flying capacitor and said selected one of said second plurality of said offset capacitors to said input terminal of said second multistage amplifier;

wherein said selected one of said first and second plurality of said offset capacitors is selected based on a value of a digital representation for an analog output.

18. A latching comparator receives an input and a reference to generate an output, comprising:

a. first and second complementary pairs of current field effect transistors, each complementary pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of said PiFET and said NiFET has;

i. a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of said PiFET and said NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for said each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein said output of the second complementary pair is coupled to said output of said latching comparator;

b. a plurality of switches operable by a control signal that alternates a setup phase and an enable phase;

c. a first capacitor and a second capacitor, each of said first and second capacitors having a first terminal and a second terminal, said second terminal of said first capacitor is connected to said input of said first complementary pair,

said output of said first complementary pair is capacitively coupled to said input of said second complementary pair;

wherein, during said setup phase of said control signal, said plurality of switches cause said reference to coupled to said first terminal of said first capacitor for capacitively coupling to said input of said first complementary pair, said first complementary pair to be self-biased by coupling said output of said first complementary pair to said input of said first complementary pair, and said second complementary pair to be self-biased by coupling said output of said second complementary pair to said input of said second complementary pair; and

during said enable phase of said control signal, said plurality of switches cause said input of said latching comparator to be coupled to said first terminal of said first capacitor for capacitively coupling to said input of the first complementary pair, and said output of said second complementary pair to be coupled to said input of said first complementary pair.

19. A latching comparator receives an input and a reference to generate an output, comprising:

a. first and second multistage amplifiers, each multistage amplifier comprises at least three complementary pairs of current field effect transistors, each complementary pair comprising a p-type current field effect transistor (PiFET) and an n-type current field effect transistor (NiFET), each of said PiFET and said NiFET has;

i. a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of said PiFET and said NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source and drain channels;

wherein, for said each complementary pair, said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form an input, said source terminal of said NiFET is connected to negative power supply and said source terminal of said PiFET is connected to positive power supply, and said drain terminals of said NiFET and said PiFET are connected together to form an output, and

wherein, for each multistage amplifier, said at least three complementary pairs are connected in series by connecting said output of a previous pair to said input of a subsequent pair of said at least three complementary pairs,

said output of the second multistage amplifier is coupled to said output of said latching comparator;

b. a plurality of switches operable by a control signal that alternates a setup phase and an enable phase;

c. a first capacitor and a second capacitor, each of said first and second capacitors having a first terminal and a second terminal, said second terminal of said first capacitor is connected to said input of said first multistage amplifier,

said output of said first complementary pair is capacitively coupled to said input of said second multistage amplifier;

wherein, during said setup phase of said control signal, said plurality of switches cause said reference to be coupled to said first terminal of said first capacitor for capacitively coupling to said input of said first multistage amplifier, said first multistage amplifier to be self-biased by coupling said output of said first multistage amplifier to said input of said first multistage amplifier, and said second multistage amplifier to be self-biased by coupling said output of said second multistage amplifier to said input of said second multistage amplifier; and

during said enable phase of said control signal, said plurality of switches cause said input of said latching comparator to be couple to said first terminal of said first capacitor for capacitively coupling to said input of the first multistage amplifier, and said output of said second multistage amplifier to be coupled to said input of said first multistage amplifier.

20. A control circuit for producing a first and second control signal, said second signal is inversion of the first control signal, comprising:

a. a first AND gate, receiving a clock signal at first and second input terminals;

b. a second AND gate, receiving a clock signal through an invertor at first and second input terminals;

c. a first alignment block for generating said first control signal, said first alignment block receives an output from said first AND gate, comprising;

i. a first invertor and a first buffer for receiving said output from said first AND gate,

ii. a second inverter and a third inverter, wherein said second inverter receives an output of said first buffer and an output of said third inverter, said third inverter receives an output of said first inverter and an output of said third inverter;

wherein said outputs of said first and second inverter, and said outputs of said first buffer and said third inverter form said first control signal;

d. a second alignment block for generating said second control signal, said said alignment block receives an output from said second AND gate, comprising;

i. a first invertor and a first buffer for receiving said output from said second AND gate,

ii. a second inverter and a third inverter, wherein said second inverter receives an output of said first buffer and an output of said third inverter, said third inverter receives an output of said first inverter and an output of said third inverter;

wherein said outputs of said first and second inverter, and said outputs of said first buffer and said third inverter form said second control signal.

21. The control circuit as recited in claim 20, wherein said outputs from said first and second alignment blocks are coupled with buffers.

22. The control circuit as recited in claim 20, wherein said clock is coupled with a buffer.