Contention-Free Dynamic Logic

• US 20180226968A1
• Filed: 04/20/2017
• Published: 08/09/2018
• Est. Priority Date: 02/05/2017
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Schaefer, Alexander W.
• Application Number:
  US15/492,249
• Publication Number:
  US 20180226968A1
• Time in Patent Office: Days
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A dynamic logic circuit includes a pull-up network coupled between a voltage supply and a dynamic node and receives a first input signal and a second input signal. A pull-down network is coupled between the dynamic node and a ground node and receives the first input signal and the second input signal. A pre-charge network is in parallel with the pull-up or pull-down network and pre-charges the dynamic node to a high or low voltage level prior to evaluation of the first and second input signals. The transistors in the pull-up network are substantially different in size than the transistors in the pull-down network.

Claims

1. An apparatus comprising:

a pull-up network coupled between a voltage supply node and a first dynamic node and coupled to receive a first input signal and a second input signal;

a pull-down network coupled between the first dynamic node and a ground node and coupled to receive the first input signal and the second input signal;

a pre-charge network coupled to receive a pre-charge signal and coupled to the first dynamic node to pre-charge the first dynamic node to a pre-charge voltage level prior to evaluation of the first and second input signals;

wherein first transistors in the pull-up network are substantially different in size than second transistors in the pull-down network;

a second pull-up network coupled between the voltage supply node and a second dynamic node, the second pull-up network connected to the first dynamic node to receive an output signal on the first dynamic node as a third input signal and to receive a fourth input signal from another source;

a second pull-down network coupled between the second dynamic node and the ground node and coupled to receive the third input signal and the fourth input signal;

a second pre-charge network coupled to receive a second pre-charge signal and coupled to the second dynamic node to pre-charge the second dynamic node to a second pre-charge voltage level prior to evaluation of the third and fourth input signals, wherein one of the first and second pre-charge voltage levels is a high voltage level and the other of the first and second pre-charge voltage levels is a low voltage level;

wherein the first transistors of the pull-up network and third transistors of the second pull-up network are substantially different in size; and

wherein substantially different in size is smaller or larger by a factor of between approximately four and approximately thirty-two.

3. The apparatus as recited in claim 1 wherein substantially different is size is smaller or larger by a factor of between approximately four and approximately sixteen.

4. The apparatus as recited in claim 1 wherein the first transistors in the pull-up network are substantially smaller than the second transistors in the pull-down network and the pre-charge network includes a pull-up transistor coupled between the voltage supply node and the first dynamic node to pre-charge the first dynamic node to a high voltage level as the pre-charge voltage level.

5. The apparatus as recited in claim 4 further comprising a footer transistor coupled between the ground node and the pull-down network and the footer transistor is coupled to receive the pre-charge signal.

6. The apparatus as recited in claim 1 wherein fourth transistors of the second pull-down network are substantially smaller than the third transistors of the second pull-up network and the second pre-charge network includes a pull-down transistor coupled between the ground node and the second dynamic node to pre-charge the first dynamic node to the low voltage level as the pre-charge voltage level.

7. The apparatus as recited in claim 6 further comprising a header transistor coupled between the voltage supply node and the second pull-up network and the header transistor is coupled to receive the second pre-charge signal.

2. (canceled)

8. (canceled)

9. (canceled)

10. A method comprising:

pre-charging a dynamic node to a pre-charge voltage level responsive to a pre-charge signal prior to evaluation of a first input signal and a second input signal;

receiving the first input signal and the second input signal in a pull-up network coupled between a voltage supply node and the dynamic node; and

receiving the first input signal and the second input signal in a pull-down network having first transistors that are substantially different in size than second transistors in the pull-up network,

supplying an output signal on the dynamic node as a third input signal to a second pull-up network coupled between the voltage supply node and a second dynamic node;

supplying a fourth input signal to the second pull-up network;

supplying the third input signal and the fourth input signal to respective third transistors of a second pull-down network coupled between the second dynamic node and the ground node, the third transistors substantially smaller or substantially larger than the second transistors; and

pre-charging the second dynamic node to a second pre-charge voltage level prior to evaluation of the third and the fourth input signals;

wherein the first and second pre-charge voltage levels are different voltage levels; and

wherein substantially different in size is smaller or larger by a factor of between approximately four and approximately thirty-two.

12. The method as recited in claim 10 wherein substantially different in size is smaller or larger by a factor of between approximately four and approximately sixteen.

13. The method as recited in claim 10 further comprising pre-charging the dynamic node to a high voltage level through a pull-up transistor coupled between the voltage supply node and the dynamic node responsive to a first value of the pre-charge signal.

14. The method as recited in claim 13 further comprising:

turning off a footer transistor coupled between the ground node and the pull-down network responsive to the first value of the pre-charge signal;

activating the footer transistor responsive to a second value of the pre-charge signal; and

turning off the pull-up transistor responsive to the second value of the pre-charge signal.

15. The method as recited in claim 10 further comprising precharging the dynamic node to a low voltage level through a pull-down transistor coupled between the ground node and the dynamic node responsive to a first value of a pre-charge signal.

16. The method as recited in claim 15 further comprising turning off a header transistor coupled between the first voltage node and the pull-up network responsive to the first value of the pre-charge signal;

activating the header transistor responsive to a second value of the pre-charge signal; and

turning off the pull-down transistor responsive to the second value of the pre-charge signal.

19. The method as recited in claim 10 further comprising evaluating the first input signal and the second input signal with the pre-charge signal deasserted.

11. (canceled)

17. (canceled)

18. (canceled)

20. (canceled)