MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

• US 20180232042A1
• Filed: 12/01/2017
• Published: 08/16/2018
• Est. Priority Date: 02/15/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kwanghyun
• Granted Patent: US 10,394,305 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Abstract

A memory system according to example embodiments of the inventive concept may include a storage device and a memory device. The storage device includes a first interface circuit configured to be connected to a processor and a second interface circuit different from the first interface circuit. The memory device includes a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be different from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area. The first memory area is accessed by the processor through the third interface circuit and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit.

Claims

1. A memory system comprising:

a storage device including a first interface circuit configured to be connected to a processor and a second interface circuit distinct from the first interface circuit; and

a memory device including a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be distinct from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area,

wherein the first memory area is accessed by the processor through the third interface circuit, and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit.

2. The memory system of claim 1, wherein the first memory area corresponds to a first memory cell array of the memory device and the second memory area corresponds to a second memory cell array of the memory device physically separated from the first memory cell array.

3. The memory system of claim 1, wherein the first memory area corresponds to first addresses allocated from the processor and the second memory area corresponds to second addresses allocated from the processor, the second addresses being different from the first addresses.

4. The memory system of claim 3, wherein the first addresses and the second addresses are reallocated in response to a request from at least one of the processor and the storage device.

5. The memory system of claim 1, wherein the memory device further comprises:

a first memory cell array including the first memory area and the second memory area; and

a second memory cell array physically separated from the first memory cell array,

wherein the first memory area corresponds to first addresses allocated from the processor and the second memory area corresponds to second addresses allocated from the processor, the second addresses being different from the first addresses.

6. The memory system of claim 5, wherein the second memory cell array is configured for access by the storage device in preference to the second memory area.

7. The memory system of claim 5, wherein the first addresses and the second addresses are reallocated in response to a request from at least one of the processor and the storage device.

8. The memory system of claim 1, wherein the storage device is configured to store meta data of the memory device generated based on a training result of the memory device.

9. The memory system of claim 8, wherein the storage device provides the meta data to the memory device through the second interface circuit and the fourth interface circuit.

10. The memory system of claim 9, wherein the memory device further comprises a mode register for storing the provided meta data.

11. The memory system of claim 1, wherein the storage device comprises a controller, the controller comprising the first interface circuit and the second interface circuit, the controller being configured to control operation of the storage device.

12. The memory system of claim 1, wherein the storage device comprises:

a controller including the first interface circuit; and

a nonvolatile memory including the second interface circuit, the controller being configured to control operation of the nonvolatile memory.

13. A method of operating a memory system including a storage device and a memory device connected to the storage device, the method comprising:

performing, by the processor, a first handshaking operation with the storage device and a second handshaking operation with the memory device;

dividing the memory device into a first memory area and a second memory area;

allocating the first memory area to first addresses;

allocating the second memory area to second addresses;

providing, by the processor, the second addresses to the storage device; and

performing, by the storage device, a third handshaking operation with the memory device.

14. The method of operating the memory system of claim 13, further comprising:

accessing the first memory area using the processor; and

accessing the second memory area using the storage device.

15. The method of operating the memory system of claim 13, further comprising:

reallocating, by the processor, the first addresses and the second addresses in response to a request of at least one of the processor and the storage device; and

providing, by the processor, the reallocated second addresses to the storage device.

16. A memory system, comprising:

a volatile main memory device comprising a first auxiliary interface circuit;

a nonvolatile storage device comprising a second auxiliary interface circuit; and

a processor component comprising a main memory controller that is configured to control operation of the volatile main memory device and a storage controller that is configured to control operation of the nonvolatile storage device;

wherein the volatile main memory device and the nonvolatile storage device are configured to communicate via the first auxiliary interface circuit and the second auxiliary interface circuit without passing through the processor component.

17. The memory system of claim 16, wherein the volatile main memory device comprises:

a memory controller interface circuit; and

a first memory cell array and a second memory cell array;

wherein the first memory cell array is configured to be accessible to the processor component via the memory controller interface circuit; and

wherein the second memory cell array is configured to be accessible to the nonvolatile storage device via the first auxiliary interface circuit and the second auxiliary interface circuit.

18. The memory system of claim 17, wherein the first memory cell array and the second memory cell arrays are physically separate components that are independently replaceable.

19. The memory system of claim 17, wherein the first memory cell array and the second memory cell array comprise a first area and a second area, respectively, of a monolithic memory cell array device;

and

wherein the processor component is configured to allocate first addresses to the first memory cell array and is configured to allocate second addresses to the second memory cell array, the first addresses being unique from the second addresses.

20. The memory system of claim 19, wherein the volatile main memory device further comprises:

a preferential memory cell array that is configured to be preferentially accessible to the nonvolatile storage device via the first auxiliary interface circuit and the second auxiliary interface circuit relative to the second area of the monolithic memory cell array device.