MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
First Claim
1. A memory system comprising:
- a storage device including a first interface circuit configured to be connected to a processor and a second interface circuit distinct from the first interface circuit; and
a memory device including a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be distinct from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area,wherein the first memory area is accessed by the processor through the third interface circuit, and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit.
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Accused Products
Abstract
A memory system according to example embodiments of the inventive concept may include a storage device and a memory device. The storage device includes a first interface circuit configured to be connected to a processor and a second interface circuit different from the first interface circuit. The memory device includes a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be different from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area. The first memory area is accessed by the processor through the third interface circuit and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit.
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Citations
20 Claims
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1. A memory system comprising:
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a storage device including a first interface circuit configured to be connected to a processor and a second interface circuit distinct from the first interface circuit; and a memory device including a third interface circuit configured to be connected to the processor based on a DRAM interface, a fourth interface circuit configured to be distinct from the third interface circuit and configured to be connected to the second interface circuit, and a random access memory divided into a first memory area and a second memory area, wherein the first memory area is accessed by the processor through the third interface circuit, and the second memory area is accessed by the storage device through the second interface circuit and the fourth interface circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a memory system including a storage device and a memory device connected to the storage device, the method comprising:
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performing, by the processor, a first handshaking operation with the storage device and a second handshaking operation with the memory device; dividing the memory device into a first memory area and a second memory area; allocating the first memory area to first addresses; allocating the second memory area to second addresses; providing, by the processor, the second addresses to the storage device; and performing, by the storage device, a third handshaking operation with the memory device. - View Dependent Claims (14, 15)
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16. A memory system, comprising:
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a volatile main memory device comprising a first auxiliary interface circuit; a nonvolatile storage device comprising a second auxiliary interface circuit; and a processor component comprising a main memory controller that is configured to control operation of the volatile main memory device and a storage controller that is configured to control operation of the nonvolatile storage device; wherein the volatile main memory device and the nonvolatile storage device are configured to communicate via the first auxiliary interface circuit and the second auxiliary interface circuit without passing through the processor component. - View Dependent Claims (17, 18, 19, 20)
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Specification