Method of Semiconductor Integrated Circuit Fabrication

• US 20180233406A1
• Filed: 04/16/2018
• Published: 08/16/2018
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Ching-Fu, Peng, Chao-Hsien, Wu, Hsien-Chang, Lee, Hsiang-Huan
• Granted Patent: US 10,453,746 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs

Abstract

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Claims

1. A device comprising:

a metal layer disposed over a substrate;

a catalyst layer disposed on the metal layer;

a plurality of carbon nanotubes (CNTs) disposed on the catalyst layer; and

a dielectric layer disposed adjacent to the plurality of CNTs.

2. The device of claim 1, wherein the substrate is a semiconductor substrate, and

wherein the dielectric layer extends to the semiconductor substrate.

3. The device of claim 1, wherein the substrate includes a conductive feature, and

wherein the metal layer physically contacts the conductive feature.

4. The device of claim 3, wherein the conductive feature includes a feature selected from the group consisting of a doped feature, a gate electrode, and a silicide feature.

5. The device of claim 1, further comprising a hard mask layer disposed over the substrate, and

wherein the metal layer includes a first portion and a second portion, the catalyst layer extending from the first portion of the metal layer and the hard mask layer extending from the second portion of the metal layer.

6. The device of claim 5, wherein the dielectric layer extends continuously from the first portion of the metal layer to the second portion of the metal layer.

7. The device of claim 1, wherein the catalyst layer includes a material selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), and molybdenum (Mo).

8. A device comprising:

a first conductive feature and second conductive feature disposed over a semiconductor substrate;

a catalyst layer disposed over the first conductive feature without being disposed over the second conductive feature;

a plurality of carbon nanotubes (CNTs) extending from the catalyst layer; and

a dielectric layer extending from the second conductive feature to at least one carbon nanotube from the plurality of CNTs.

9. The device of claim 8, further comprising a third conductive feature disposed on a first side of the first conductive feature, wherein the second conductive feature is disposed on a second side of the first conductive feature, the second side being opposite the first side.

10. The device of claim 9, wherein the dielectric layer extends from the third conductive feature to at least one carbon nanotube from the plurality of CNTs.

11. The device of claim 8, further comprising a material layer disposed directly on a top surface of the second conductive feature, and

wherein the dielectric layer is disposed over the second conductive feature,

wherein the material layer prevents the dielectric layer from interfacing with top surface of the second conductive feature.

12. The device of claim 11, wherein the material layer includes a carbon film.

13. The device of claim 11, wherein the material layer includes a nitride layer.

14. The device of claim 8, wherein the first conductive feature has a first sidewall surface and the catalyst layer has a second sidewall surface that interfaces the first sidewall surface of the first conductive feature, and

wherein the dielectric layer completely covers the first sidewall surface of the first conductive feature and the second sidewall surface of the catalyst layer.

15. A device comprising:

a conductive layer disposed over a substrate;

a catalyst layer disposed on the conductive layer;

a plurality of carbon nanotubes (CNTs) extending from the catalyst layer; and

a dielectric layer extending from the substrate to at least one of the CNTs.

16. The device of claim 15, further comprising a interconnect structure disposed on the substrate, and

wherein the conductive layer interfaces with the interconnect structure.

17. The device of claim 15, wherein the conductive layer has a sidewall surface and the dielectric layer is disposed directly on the sidewall surface of the conductive layer.

18. The device of claim 15, wherein the conductive layer includes a first portion and a second portion that are spaced apart from each other by the dielectric layer.

19. The device of claim 18, wherein the first portion has a first top surface facing away from the substrate and the second portion has a second top surface facing away from the substrate, and

wherein the catalyst layer is disposed directly on the first top surface of the first portion and the second top surface of the second portion is free of the catalyst layer.

20. The device of claim 15, wherein the dielectric layer physically contacts the conductive layer and the catalyst layer.