STRAINED SEMICONDUCTOR DEVICE

• US 20180233560A1
• Filed: 04/11/2018
• Published: 08/16/2018
• Est. Priority Date: 06/28/2016
• Status: Active Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: CHENG, Kangguo, XU, Peng
• Application Number:
  US15/950,231
• Publication Number:
  US 20180233560A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility

Abstract

A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.

Claims

1. A semiconductor device comprising;

a first semiconductor fin having a first width, the first semiconductor fin arranged on a first portion of a strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width;

a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width;

a gate stack arranged over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin.

2. The device of claim 1, wherein the first width is greater than the second width.

3. The device of claim 1, wherein the third width is less than the first width.

4. The device of claim 1, wherein the first semiconductor fin comprises a tensile strained material.

5. The device of claim 4, wherein the second semiconductor fin comprises a compressive strained material.

6. The device of claim 1, wherein the strain relaxation buffer layer is an epitaxial layer.

7. The device of claim 1, wherein the strain relaxation buffer layer includes a concentration of germanium.

8. The device of claim 1, wherein the strain relaxation buffer layer includes silicon germanium.

9. The device of claim 4, wherein the tensile strained material includes an epitaxially grown silicon material.

10. The device of claim 1, wherein the first and second semiconductor fins are on a substrate.

11. The device of claim 10, wherein the substrate includes silicon carbide.

12. The device of claim 10, wherein the substrate includes silicon-germanium-carbon.

13. The device of claim 5, wherein the compressive strained material includes an epitaxially grown silicon germanium material.

14. The device of claim 5, wherein the tensile strained material is different from the compressive strained material.

15. The device of claim 5, wherein a concentration of germanium in the compressive strained material is greater than a concentration of germanium in the strain relaxation buffer layer.

16. The device of claim 1, wherein the gate stack is a replacement metal gate stack.

17. The device of claim 1, wherein the gate stack comprises one or more dielectric materials.

18. The device of claim 17, wherein the gate stack comprises one or more workfunction metals on the one or more dielectric materials.

19. The device of claim 18, wherein one or more metal gate conductor materials are formed on the one or more workfunction metals.

20. The device of claim 10, wherein the substrate includes silicon.