System, Apparatus And Method For Providing A Unique Identifier In A Fuseless Semiconductor Device

• US 20180234258A1
• Filed: 02/16/2017
• Published: 08/16/2018
• Est. Priority Date: 02/16/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Peffers, Simon N., Gulley, Sean M., Gopal, Vinodh, Mathew, Sanu K.
• Granted Patent: US 10,462,110 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 16/00 Information retrieval; Database structures therefor; File system structures therefor
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/0876 based on the identity of the terminal or configuration, e.g. MAC address, hardware or software configuration or device fingerprint
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
• CPC Class Codes: H04L 9/3278 using physically unclonable functions [PUF]

Abstract

In one embodiment, an apparatus includes: a device having a physically unclonable function (PUF) circuit including a plurality of PUF cells to generate a PUF sample responsive to at least one control signal; a controller coupled to the device, the controller to send the at least one control signal to the PUF circuit and to receive a plurality of PUF samples from the PUF circuit; a buffer having a plurality of entries each to store at least one of the plurality of PUF samples; and a filter to filter the plurality of PUF samples to output a filtered value, wherein the controller is to generate a unique identifier for the device based at least in part on the filtered value. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a device having a physically unclonable function (PUF) circuit including a plurality of PUF cells to generate a PUF sample responsive to at least one control signal;

a controller coupled to the device, the controller to send the at least one control signal to the PUF circuit and to receive a plurality of PUF samples from the PUF circuit;

a buffer having a plurality of entries each to store at least one of the plurality of PUF samples; and

a filter to filter the plurality of PUF samples to output a filtered value, wherein the controller is to generate a unique identifier for the device based at least in part on the filtered value.

2. The apparatus of claim 1, wherein the device comprises a fuseless integrated circuit.

3. The apparatus of claim 2, wherein the fuseless integrated circuit comprises an Internet of Things (IoT) sensor device.

4. The apparatus of claim 1, wherein the controller is, in response to a determination that a number of the plurality of PUF samples meets a threshold number, to cause the plurality of PUF samples to be provided to the filter.

5. The apparatus of claim 4, wherein the filter is to determine a majority vote for each of a plurality of bits of the plurality of PUF samples, the filtered value corresponding to the majority vote for each of the plurality of bits.

6. The apparatus of claim 5, wherein the filter is to mask a first bit of the plurality of bits when a count of first values of the first bit in the plurality of PUF samples is not within a threshold range.

7. The apparatus of claim 4, wherein the controller is to dynamically adjust the threshold number.

8. The apparatus of claim 1, wherein the device is to use the unique identifier as a private key.

9. The apparatus of claim 1, wherein the device further comprises a cryptographic circuit to sign a data block with the unique identifier.

10. The apparatus of claim 1, wherein at least some of the plurality of PUF cells comprise a cross-coupled inverter circuit.

11. The apparatus of claim 1, wherein at least some of the plurality of PUF cells comprise a ring of inverters to generate a clock pattern.

12. The apparatus of claim 1, wherein the device comprises a microcontroller to use the unique identifier to perform a challenge-response protocol with a verifier.

13. The apparatus of claim 1, further comprising a power controller to:

access an entry in a characterization table using the unique identifier; and

control one or more operating parameters of the device based on information stored in the entry.

14. A non-transitory machine-readable medium having stored thereon one or more instructions, which if performed by a machine, cause the machine to perform a method comprising:

requesting a physically unclonable function (PUF) circuit of a first integrated circuit to generate a PUF sample;

receiving the PUF sample from the PUF circuit and storing the PUF sample in an entry of a sample storage; and

responsive to determining that a number of PUF samples stored in the sample storage meets a threshold, filtering the plurality of PUF samples according to at least one filter technique to generate a unique identifier for the first integrated circuit based at least in part on the filtered plurality of PUF samples.

15. The non-transitory machine-readable medium of claim 14, wherein the method further comprises:

causing the first integrated circuit to operate at an operating point;

collecting metric information from the first integrated circuit during operation at the operating point; and

storing at least some of the metric information in a database in association with the unique identifier.

16. The non-transitory machine-readable medium of claim 14, wherein the method further comprises:

receiving, in the first integrated circuit, a challenge from a verifier device;

signing a challenge response, in the first integrated circuit, with the unique identifier; and

sending the signed challenge response to the verifier device.

17. The non-transitory machine-readable medium of claim 14, wherein the method further comprises:

generating a message, in the first integrated circuit, the message including at least first sensor information;

encrypting the message, in the first integrated circuit, using the unique identifier; and

sending the encrypted message to a destination device.

18. A system comprising:

a first integrated circuit including at least one accelerator circuit and a physically unclonable function (PUF) circuit including a plurality of PUF cells to generate a PUF sample responsive to at least one control signal; and

a controller coupled to the first integrated circuit to provide a workload to the first integrated circuit and to control at least one operating parameter of the first integrated circuit, the controller to;

send a plurality of sample signals to the first integrated circuit to enable receipt in the controller of a plurality of PUF samples for the first integrated circuit;

buffer the plurality of PUF samples in at least one storage;

filter the plurality of PUF samples according to a plurality of filter techniques to output a filtered value; and

identify the first integrated circuit based at least in part on the filtered value.

19. The system of claim 18, wherein the controller is to:

access an entry in a characterization table using the filtered value; and

control the at least one operating parameter of the first integrated circuit based on information stored in the entry.

20. The system of claim 18, wherein the system comprises a server having at least one processor, a mass storage and a communication interface, the controller coupled to the at least one processor via the communication interface, and wherein the first integrated circuit comprises a fuseless semiconductor device and the at least one accelerator circuit comprises a cryptographic circuit.

21. The system of claim 18, wherein the controller is to cause the PUF circuit to be power cycled a plurality of times during operation of the first integrated circuit in response to the plurality of sample signals to enable the receipt of the plurality of PUF samples, and to thereafter cause the PUF circuit to be power gated after the first integrated circuit is identified based at least in part on the filtered value.