STACKED BODY

• US 20180240797A1
• Filed: 08/09/2016
• Published: 08/23/2018
• Est. Priority Date: 09/01/2015
• Status: Active Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: YOKOYAMA, Takashi, UMEBAYASHI, Taku
• Application Number:
  US15/754,054
• Publication Number:
  US 20180240797A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/07 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14627 : Microlenses
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 : Back illuminated imager structures
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type

Abstract

A stacked body according to an embodiment of the present technology includes: a plurality of transistors; a first substrate; and a second substrate that is stacked with the first substrate and is electrically coupled to the first substrate, in which a first transistor to be driven at a first driving voltage being a lowest voltage of the plurality of transistors is provided only in the first substrate of the first substrate and the second substrate to form a first circuit.

Claims

1. A stacked body, comprising:

a plurality of transistors;

a first substrate; and

a second substrate that is stacked with the first substrate and is electrically coupled to the first substrate,

wherein a first transistor to be driven at a first driving voltage being a lowest voltage of the plurality of transistors is provided only in the first substrate of the first substrate and the second substrate to form a first circuit.

2. The stacked body according to claim 1, wherein a second circuit including a second transistor to be driven at a second driving voltage higher than the first driving voltage of the plurality of transistors is formed in the second substrate.

3. The stacked body according to claim 2, wherein the first circuit further includes a third transistor to be driven at a third driving voltage higher than the first driving voltage and lower than the second driving voltage.

4. The stacked body according to claim 2, wherein

each of the first transistor and the second transistor includes a gate electrode, a pair of source-drain electrodes, a semiconductor film that forms a channel, and a gate insulating film provided between the gate electrode and the semiconductor film, and

a thickness of the gate insulating film in the second transistor is thicker than a thickness of the gate insulating film in the first transistor.

5. The stacked body according to claim 1, wherein a semiconductor layer of the first transistor includes one of silicon (Si), germanium (Ge), a compound semiconductor, and graphene.

6. The stacked body according to claim 1, wherein the first transistor is one or more kinds of a transistor using a high dielectric constant film/metal gate (high-K/metal gate) technology, a fully-depleted transistor, and a T-FET.

7. The stacked body according to claim 2, wherein the first circuit is a logic circuit, and the second circuit is an analog circuit.

8. The stacked body according to claim 1, wherein the first substrate and the second substrate are electrically coupled to each other through surface-bonding or a through electrode.

9. The stacked body according to claim 1, wherein one or more circuits having a communication function that allows for transmission and reception in a plurality of frequency bands are mounted in the second substrate.

10. The stacked body according to claim 9, wherein the circuit having a communication function that allows for transmission and reception in a plurality of frequency bands includes an RF front end unit including a transmit-receive switch and a power amplifier and an RF-IC unit including a low noise amplifier and a transmit-receive mixer.

11. The stacked body according to claim 10, wherein in a case where the RF front end unit and the RF-IC unit include a third circuit including a third transistor having a driving voltage lower than the driving voltage of the second transistor provided in the second substrate and higher than the driving voltage of the first transistor, the third circuit is provided in the first substrate.

12. The stacked body according to claim 1, wherein at least a circuit having an image sensor function, a circuit having a temperature sensor function, a circuit having a gravity sensor function, and a circuit having a position sensor function are mounted in the second substrate.

13. The stacked body according to claim 1, wherein

a circuit of one or more kinds of interface standards is mounted in the second substrate, and

the interface standards are an MIPI, the MIPI includes a digital controller and a PHY unit, and the digital controller and the PHY unit are respectively mounted in the first substrate and the second substrate.

14. The staked body according to claim 1, wherein a logic circuit, an analog circuit, and a pixel unit are included, the analog circuit, the logic circuit, and the pixel unit are respectively mounted in the second substrate, the first substrate, and the third substrate.

15. The stacked body according to claim 2, wherein the second substrate includes a core substrate, the second transistor is formed on a first surface of the core substrate, a functional element is formed on a second surface facing the first surface, and the functional element is one or more kinds of an inductor, a capacitor, a non-volatile element, and an antenna.

16. The stacked body according to claim 15, wherein a shield structure is included between the first substrate and the functional element, and the shield structure is a concave-convex structure provided on the second surface of the core substrate of the second substrate, or a shield layer including a magnetic material.

17. The stacked body according to claim 15, wherein

the second substrate includes an RF front end unit including a transmit-receive switch and a power amplifier, and

the antenna is provided at a position facing the RF front end unit.

18. The stacked body according to claim 15, wherein the first substrate includes a core substrate, and the first transistor is included on a first surface of the core substrate, and one or more kinds of the functional element and the non-volatile element are formed on a second surface facing the first surface.

19. The stacked body according to claim 1, wherein a programmable circuit or an element is mounted in the first substrate, and the programmable circuit includes a FPGA (field-programmable gate array) and a CPU (central processing unit).

20. The stacked body according to claim 15, wherein an extraction electrode is provided on a surface opposite to a surface facing the second substrate of the first substrate.

21. The stacked body according to claim 15, wherein a compound semiconductor substrate is used as the core substrate in one or both of the second substrate and a fourth substrate.

22. The stacked body according to claim 21, wherein the compound semiconductor substrate is in contact with an insulating layer.

23. The stacked body according to claim 21, wherein a low noise amplifier is mounted in the first substrate, and a power amplifier is mounted in the fourth substrate.