Techniques for VFET Top Source/Drain Epitaxy

• US 20180240873A1
• Filed: 02/21/2017
• Published: 08/23/2018
• Est. Priority Date: 02/21/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Chi, Cheng, Liu, Chi-Chun, Xie, Ruilong, Yamashita, Tenko, Yeh, Chun-Chen
• Granted Patent: US 10,199,464 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Techniques for VFET top source and drain epitaxy are provided. In one aspect, a method of forming a VFET includes: patterning a fin to form a bottom source/drain region and a fin channel of the VFET; forming bottom spacers on the bottom source/drain region; depositing a high-κ gate dielectric onto the bottom spacers and along sidewalls of the fin channel; forming gates over the bottom spacers; forming top spacers on the gates; partially recessing the fin channel to create a trench between the top spacers; forming a nitride liner along sidewalls of the trench; fully recessing the fin channel through the trench such that side portions of the fin channel remain intact; and forming a doped epitaxial top source and drain region over the fin channel. Methods not requiring a nitride liner and VFET formed using the present techniques are also provided.

Claims

1. A method of forming a vertical field-effect transistor (VFET), comprising the steps of:

patterning a fin in a stack comprising a doped epitaxial layer disposed on a substrate, and an intrinsic layer disposed on the doped epitaxial layer, wherein the doped epitaxial layer as patterned forms a bottom source and drain region of the VFET, and wherein the intrinsic layer as patterned forms a fin channel of the VFET;

forming bottom spacers on the bottom source and drain region on opposite sides of the fin channel;

depositing a high-κ

gate dielectric onto the bottom spacers and along sidewalls of the fin channel;

forming gates over the bottom spacers on opposite sides of the fin channel, wherein the gates are separated from the fin channel by the high-κ

gate dielectric;

forming top spacers on the gates on opposite sides of the fin channel;

partially recessing the fin channel to create a trench between the top spacers;

forming a nitride liner along sidewalls of the trench;

fully recessing the fin channel through the trench, wherein the nitride liner reduces a width of the trench such that side portions of the fin channel remain intact during the fully recessing that cover the high-κ

gate dielectric; and

forming a doped epitaxial top source and drain region in the trench over the fin channel.

2. The method of claim 1, further comprising the steps of:

forming a patterned fin hardmask on the stack; and

using the patterned fin hardmask to pattern the fin in the stack.

3. The method of claim 2, further comprising the steps of:

depositing a spacer material on top of the gates and the patterned fin hardmask;

depositing a filler dielectric surrounding the bottom spacers, the fin channel, the gates and the high-κ

gate dielectric, and the spacer material;

recessing the filler dielectric;

removing the spacer material from over the fin channel to form the top spacers on opposite sides of the fin channel; and

removing the patterned fin mask.

4. The method of claim 1, wherein during the partially recessing of the fin channel, a top of the fin channel remains between the top spacers.

5. The method of claim 1, wherein the nitride liner reduces a width of the trench to be less than a width of the fin channel.

6. The method of claim 1, wherein during the fully recessing of the fin channel an exposed center portion of the fin channel is removed.

7. The method of claim 1, wherein during the fully recessing of the fin channel, a center portion of the fin channel is recessed below a top of the gates.

8. The method of claim 1, wherein the side portions of the fin channel that remain intact fully covering the high-κ

gate dielectric have a thickness of from about 5 nm to about 10 nm, and ranges therebetween.

9. The method of claim 1, further comprising the step of:

annealing the doped epitaxial top source and drain region to diffuse dopants from the doped epitaxial top source and drain region into the side portions of the fin channel covering the high-κ

gate dielectric.

10. The method of claim 1, wherein the step of forming the nitride liner along the sidewalls of the trench includes the steps of:

depositing the nitride liner into and lining a bottom and the sidewalls of the trench; and

removing the nitride liner from horizontal surfaces including the bottom of the trench.

11. A method of forming a VFET, comprising the steps of:

patterning a fin in a stack comprising a doped epitaxial layer disposed on a substrate, and an intrinsic layer disposed on the doped epitaxial layer, wherein the doped epitaxial layer as patterned forms a bottom source and drain region of the VFET, and wherein the intrinsic layer as patterned forms a fin channel of the VFET;

forming bottom spacers on the bottom source and drain region on opposite sides of the fin channel;

depositing a high-κ

gate dielectric onto the bottom spacers and along sidewalls of the fin channel;

forming gates over the bottom spacers on opposite sides of the fin channel, wherein the gates are separated from the fin channel by the high-κ

gate dielectric;

forming top spacers i) on the gates on opposite sides of the fin channel, and ii) over the fin channel;

thinning a region of the fin channel between the top spacers;

depositing a filler dielectric surrounding the bottom spacers, the fin channel, the gates and the high-κ

gate dielectric, and the top spacers;

removing the top spacer from over the fin channel forming a trench in the filler dielectric;

recessing the fin channel through the trench, wherein the trench has a width that is greater than a width of the thinned region of the fin channel such that side portions of the fin channel remain intact during the recessing that cover the high-κ

gate dielectric; and

forming a doped epitaxial top source and drain region in the trench over the fin channel.

12. The method of claim 11, further comprising the steps of:

forming a patterned fin hardmask on the stack; and

using the patterned fin hardmask to pattern the fin in the stack.

13. The method of claim 12, further comprising the steps of:

depositing a spacer material over of the gates and the fin channel; and

removing the spacer material from the sidewalls of the fin channel.

14. The method of claim 13, further comprising the step of:

depositing the spacer material as a non-conformal layer over the gates and the fin channel, wherein the spacer material on top of the gates and the fin channel has a thickness t1 and the spacer material on the sidewalls of the fin channel has a thickness t2, and wherein t1>

t2.

15. The method of claim 12, further comprising the step of:

removing the patterned fin hardmask from over the fin channel prior to the recessing.

16. The method of claim 11, wherein during the recessing of the fin channel, a center portion of the fin channel is recessed below a top of the gates.

17. The method of claim 11, further comprising the step of:

annealing the doped epitaxial top source and drain region to diffuse dopants from the doped epitaxial top source and drain region into the side portions of the fin channel covering the high-κ

gate dielectric.

18. A VFET, comprising:

a doped epitaxial bottom source and drain region;

a fin channel disposed on the doped epitaxial bottom source and drain region;

bottom spacers disposed on the bottom source and drain region on opposite sides of the fin channel;

a high-κ

gate dielectric disposed on the bottom spacers and along sidewalls of the fin channel;

gates over the bottom spacers on opposite sides of the fin channel, wherein the gates are separated from the fin channel by the high-κ

gate dielectric, wherein a center portion of the fin channel is recessed below a top of the gates, and wherein side portions of the fin channel are un-recessed and remain intact covering the high-κ

gate dielectric;

top spacers disposed on the gates on opposite sides of the fin channel; and

a doped epitaxial top source and drain region in the trench over the fin channel.

19. The VFET of claim 18, wherein the doped epitaxial top source and drain region is T-shaped.

20. The VFET of claim 18, wherein the side portions of the fin channel have a thickness of from about 5 nm to about 10 nm, and ranges therebetween.

21. The VFET of claim 18, further comprising:

a filler dielectric surrounding the bottom spacers, the fin channel, the gates and the high-κ

gate dielectric, and the top spacers.