METHOD FOR MANUFACTURING A TRANSISTOR AND METHOD FOR MANUFACTURING A RING OSCILLATOR USING THE SAME

• US 20180240888A1
• Filed: 11/28/2017
• Published: 08/23/2018
• Est. Priority Date: 02/20/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: OH, Dong Yean
• Granted Patent: US 10,297,674 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

In a method for manufacturing a transistor, a gate structure may be formed on a semiconductor substrate. A first material layer may be formed on the gate structure to expose an upper sidewall of the gate structure. A spacer including a second material layer may be formed on the upper sidewall of the gate structure. The first material layer may be isotropically etched using the spacer as an etch mask to form a space. An insulating interlayer may be formed on the semiconductor substrate. The insulating interlayer may not be formed in the space.

Claims

1. A method for manufacturing a transistor, the method comprising:

forming a gate structure on a semiconductor substrate;

forming a first material layer including a first material to expose an upper sidewall of the gate structure;

forming a spacer including a second material on the upper sidewall of the gate structure;

isotropically etching the first material layer using the spacer as an etch mask to form a space; and

forming an insulating interlayer over the semiconductor substrate including the gate structure,

wherein the insulating interlayer is not formed in the space so that an air spacer is formed in the space.

2. The method of claim 1, wherein the forming of the first material layer comprises:

forming the first material layer on the semiconductor substrate and the gate structure; and

anisotropically etching the first material layer to form a spacer including the first material having a height lower than a height of the gate structure.

3. The method of claim 2, further comprising:

forming planarizing layer on the spacer including the first material between the forming of the spacer including the first material and the forming of the spacer including the second material; and

selectively removing the planarizing layer to expose a sidewall of the spacer including the first material after the forming of the spacer including the second material.

4. The method of claim 3, wherein the planarizing layer comprises a liquefied insulating layer including a spin on glass (SOG) or a spin on carbon (SOC).

5. The method of claim 1, wherein the forming of the first material layer comprises:

forming the first material layer on the semiconductor substrate to fill up a space between the gate structures; and

recessing the first material layer to expose the upper sidewall of the gate structure.

6. The method of claim 5, further comprising anisotropically etching the first material layer using the spacer including the second material as an etch mask between the forming of the spacer including the second material and the forming of the space.

7. The method of claim 1, wherein the forming of the gate structure comprises:

forming a gate insulating layer on the semiconductor substrate;

forming a gate conductive layer on the gate insulating layer;

forming a hard mask layer on the gate conductive layer; and

patterning the hard mask layer and the gate conductive layer.

8. The method of claim 1, further comprising forming a first liner on the semiconductor substrate and the gate structure between the forming of the gate structure and the forming of the first material layer.

9. The method of claim 8, wherein the first liner comprises silicon nitride.

10. The method of claim 8, wherein the first material has an etching selectivity with respect to a material of the first liner and the second material.

11. The method of claim 10, wherein the first material comprises silicon germanium.

12. The method of claim 11, wherein the second material has an etching selectivity with respect to the material of the first liner and the first material.

13. The method of claim 12, wherein the second material comprises silicon oxide.

14. The method of claim 8, further comprising forming a second liner on the semiconductor substrate, an inner surface of the space, a surface of the spacer including the second material and a surface of the first liner between the forming of the space and the forming of the insulating interlayer.

15. The method of claim 1, wherein the forming of the insulating interlayer comprises anisotropically depositing the insulating interlayer under a condition that a deposition speed in a direction substantially perpendicular to a surface of the semiconductor substrate is faster than a deposition speed in a direction substantially parallel to the surface of the semiconductor substrate.

16. A method for manufacturing a transistor, the method comprising:

forming a gate structure on a semiconductor substrate;

forming a first spacer on a lower sidewall of the gate structure;

forming a second spacer over the first spacer;

selectively removing the first spacer by supplying an etchant through an exposed side surface of the first spacer to form a space under the second spacer; and

forming an insulating interlayer over the semiconductor substrate including the gate structure,

wherein the insulating interlayer is not formed in the space so that an air spacer is formed in the space.

17. The method of claim 16, wherein the first and second spacers have an etching selectivity with respect to a specific etchant.

18. The method of claim 16, wherein the forming of the insulating interlayer comprises controlling a deposition speed, a pressure and a gas supply amount to set a deposition speed in a direction substantially perpendicular to a surface of the semiconductor substrate faster than a deposition speed in a direction substantially parallel to the surface of the semiconductor substrate.

19. A method for manufacturing a ring oscillator including serially connected inverters, each inverter including an NMOS transistor and a PMOS transistor, the method comprising:

forming a gate structure on a semiconductor substrate;

forming a first spacer on a lower sidewall of the gate structure;

forming a second spacer over the first spacer;

selectively removing the first spacer by supplying an etchant through an exposed side surface of the first spacer to form a space under the second spacer; and

forming an insulating interlayer over the semiconductor substrate including the gate structure,

wherein the insulating interlayer is not formed in the space so that an air spacer is formed in the space.

20. The method of claim 19, wherein the first and second spacers have an etching selectivity with respect to a specific etchant.