Method and Structure for FinFET Devices

• US 20180240909A1
• Filed: 04/23/2018
• Published: 08/23/2018
• Est. Priority Date: 01/27/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Kuo-Yin, Tsai, Teng-Chun, Lin, Po-Yu
• Granted Patent: US 10,164,102 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Claims

1. A method, comprising:

providing a semiconductor substrate that includes a first region containing a dopant of a first type and a second region containing a dopant of a second type that is opposite the first type;

forming a first layer on the first region and the second region, wherein the first layer contains a dopant of the second type;

recessing a portion of the first layer disposed over the first region;

forming a second layer on the recessed portion of the first layer disposed over the first region, wherein the second layer contains a dopant of the first type; and

performing a first Chemical Mechanical Planarization (CMP) process to planarize the first layer and the second layer.

2. The method of claim 1 further comprising:

performing an etching process to form a first fin that contains the first region, the first layer, and the second layer and to form a second fin that contains the second region and the first layer.

3. The method of claim 1, wherein the second layer physically contacts a top surface of the recessed portion of the first layer and a side surface of the first layer.

4. The method of claim 1, wherein the forming of the second layer forms the second layer to extend above a top surface of the first layer.

5. The method of claim 1 further comprising:

forming a hard mask on the first layer; and

removing a first portion of the hard mask on the first region such that a second portion of the hard mask remains on the first layer on the second region.

6. The method of claim 5, wherein the forming of the second layer on the recessed portion of the first layer forms the second layer on a side surface and a top surface of the second portion of the hard mask.

7. The method of claim 5 further comprising:

performing a second CMP process prior to the first CMP process to remove the second portion of the hard mask.

8. The method of claim 7, wherein the second CMP process is configured to remove the second portion of the hard mask at a greater rate than the second layer.

9. The method of claim 5, wherein the forming of the second layer forms the second layer such that a first portion of a top surface of the second layer is below a top surface of the hard mask and a second portion of the top surface of the second layer is above the top surface of the hard mask.

10. A method comprising:

providing a substrate having a first doped region and a second doped region of opposite dopant types;

depositing a first semiconductor layer such that a first portion is on the first doped region and a second portion is on the second doped region;

thinning the first portion of the first semiconductor layer;

depositing a second semiconductor layer over the first portion of the first semiconductor layer;

performing a first Chemical Mechanical Planarization (CMP) process to form a substantially planar surface including a topmost surface of the second semiconductor layer and a topmost surface of the second portion of the first semiconductor layer; and

etching to form a first fin containing the first doped region, the first semiconductor layer, and the second semiconductor layer and to form a second fin containing the second doped region and the first semiconductor layer.

11. The method of claim 10, wherein the depositing of the second semiconductor layer is such that the second semiconductor layer physically contacts a topmost surface of the first portion of the first semiconductor layer and a side surface of the second portion of the first semiconductor layer.

12. The method of claim 10, wherein the second semiconductor layer extends above the topmost surface of the second portion of the first semiconductor layer prior to the first CMP process.

13. The method of claim 10 further comprising:

forming a hard mask on the first portion and the second portion of the first semiconductor layer; and

removing the hard mask from the first portion of the first semiconductor layer such that the hard mask remains on the second portion of the first semiconductor layer.

14. The method of claim 13, wherein the second semiconductor layer is deposited on and beside the hard mask.

15. The method of claim 14 further comprising:

performing a second CMP process to remove the second semiconductor layer from the hard mask and to remove the hard mask.

16. A method comprising:

providing a substrate having a first doped region of a first dopant type and a second doped region of a second dopant type that is opposite the first dopant type;

forming a first semiconductor layer that includes a dopant of the second dopant type on the first doped region and the second doped region;

recessing the first semiconductor layer over the first doped region;

forming a second semiconductor layer that includes a dopant of the first dopant type over the first doped region; and

etching to form a first set of fins containing the first doped region, the first semiconductor layer, and the second semiconductor layer and to form a second set of fins containing the second doped region and the first semiconductor layer.

17. The method of claim 16, wherein the forming of the second semiconductor layer includes epitaxially depositing the second semiconductor layer on a top surface of the first semiconductor layer over the first doped region and on a side surface of the first semiconductor layer.

18. The method of claim 16, wherein the forming of the second semiconductor layer includes in-situ doping of the second semiconductor layer during the forming.

19. The method of claim 16, wherein the recessing of the first semiconductor layer over the first doped region includes:

forming a hard mask on the first semiconductor layer; and

patterning the hard mask to expose the first semiconductor layer over the first doped region.

20. The method of claim 19, wherein the forming of the second semiconductor layer forms the second semiconductor layer on the hard mask.