HIGH-ELECTRON-MOBILITY TRANSISTORS WITH HETEROJUNCTION DOPANT DIFFUSION BARRIER
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Abstract
III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.
12 Citations
44 Claims
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1-22. -22. (canceled)
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23. A transistor, comprising:
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an active region within a III-V semiconductor fin; and a sub-fin between the fin and a substrate, wherein the sub-fin further comprises; a first sub-fin layer of III-V semiconductor material over the substrate; a second sub-fin layer of III-V semiconductor material over the first sub-fin layer; and a third sub-fin layer of III-V semiconductor material between the first and second sub-fin layers, wherein the third layer is of a III-V alloy composition associated with a wider band gap than that of the first and second sub-fin layers. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A device including integrated circuitry, comprising:
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a plurality of n-type transistors, each including; an active region in a III-V semiconductor fin between source and drain region; a gate electrode over at least a portion of the active region; and source and drain contacts coupled to the source and drain regions, wherein; a sub-fin is disposed between the fin and a silicon substrate, the sub-fin further comprising; a first sub-fin layer of III-V semiconductor material over the substrate; a second sub-fin layer of III-V semiconductor material over the first sub-fin layer; and a third sub-fin layer of III-V semiconductor material between the first and second sub-fin layers, wherein the third layer is of a III-V alloy composition associated with a band gap having a conduction band offset (CBO) from that of the first sub-fin layer; and a plurality of p-type transistors electrically coupled to the plurality of n-type transistors. - View Dependent Claims (36, 37)
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38. A method of forming a transistor, the method comprising:
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receiving a silicon substrate; epitaxially growing a first thickness of III-V semiconductor material over a seeding surface of the substrate; epitaxially growing a second thickness III-V semiconductor material over the first thickness; epitaxially growing a third thickness of III-V semiconductor material over the second thickness, wherein the third thickness is of a III-V alloy composition associated with a band gap wider than that of the first thickness; and forming an active region of the transistor in a fourth thickness of III-V semiconductor material that is separated from the substrate by at least the first, second and third thicknesses of III-V semiconductor material. - View Dependent Claims (39, 40, 41, 42, 43, 44)
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Specification