CURRENT IN-RUSH MITIGATION FOR POWER-UP OF EMBEDDED MEMORIES

• US 20180253129A1
• Filed: 03/03/2017
• Published: 09/06/2018
• Est. Priority Date: 03/03/2017
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Singh, Harmander, Weyland, Sebastien, Venkumahanti, Suresh Kumar
• Granted Patent: US 10,353,447 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.

Claims

1. An integrated circuit, comprising:

a plurality of memory arrays, each memory array including a plurality of memory banks;

a logic circuit configured to decode a memory configuration signal to determine a memory array power-up sequence for at least a subset of the memory arrays, wherein the logic circuit is further configured to successively enable the memory arrays in the subset according to the memory array power-up sequence; and

a delay circuit configured to successively trigger each memory bank in an enabled one of the memory arrays such that the memory banks in the enabled memory array power-on according to a memory bank power-on sequence.

2. The integrated circuit of claim 1, wherein the delay circuit is further configured to trigger an initial memory bank in the enabled memory array without a delay and to successively trigger a remainder of the memory banks in the enabled memory array such that a delay separates successive ones of the memory banks triggered according to the memory bank power-on sequence.

3. The integrated circuit of claim 2, wherein the delay is a programmable delay configured in the delay circuit responsive to a delay configuration signal.

4. The integrated circuit of claim 2, wherein the delay circuit is configured to determine the delay responsive to cycles of a clock signal.

5. The integrated circuit of claim 1, wherein the logic circuit comprises a finite state machine, and wherein the memory configuration signal comprises a plurality of configuration bits.

6. The integrated circuit of claim 1, wherein the subset of the memory arrays equals the plurality of memory arrays such that the memory array power-up sequence defines a power-up sequence for all the memory arrays in the plurality of memory arrays.

7. The integrated circuit of claim 1, wherein the subset of the memory arrays does not include all the memory arrays in the plurality of memory arrays.

8. The integrated circuit of claim 1, wherein each memory bank associates with a corresponding register, and wherein the logic circuit is configured to set a data input for each memory bank'"'"'s corresponding register according to the memory bank power-up sequence.

9. The integrated circuit of claim 1, wherein the delay circuit is configured to set a clock input for each memory bank'"'"'s corresponding register to successively trigger each bank.

10. The integrated circuit of claim 4, wherein the delay is a programmable delay, and wherein the delay circuit is configured to determine the programmable delay responsive to a count of selected edges in the clock signal.

11. The integrated circuit of claim 10, wherein the programmable delay equals a period of the clock signal.

12. The integrated circuit of claim 10, wherein the programmable delay equals a plurality of periods of the clock signal.

13. The integrated circuit of claim 10, wherein the programmable delay equals one half of a period for the clock signal.

14. A method, comprising:

responsive to a first configuration signal, determining a memory array power-up sequence for a plurality of memory arrays in an integrated circuit;

successively enabling each memory array according to the memory array power-up sequence, wherein each memory array includes an initial memory bank and a plurality of remaining memory banks;

triggering the initial memory bank in an enabled one of the memory arrays to power up; and

following the triggering of the initial memory bank, successively triggering each remaining memory bank to power-up in the enabled memory array according to a memory bank power-up sequence.

15. The method of claim 14, wherein the successive triggering of each remaining memory bank occurs after a delay.

16. The method of claim 15, wherein the delay is a programmable delay, the method further comprising determining the programmable delay responsive to a second configuration signal.

17. The method of claim 15, further comprising determining the memory bank power-up sequence responsive to the first configuration signal.

18. The method of claim 15, further comprising counting successive edges of a clock signal to determine the delay.

19. An integrated circuit, comprising:

a plurality of memory arrays, each memory array including a plurality of memory banks; and

means for successively enabling each memory array according to a programmable memory array power-up sequence and for successively triggering each memory bank in each enabled memory array to power-up according to a memory bank power-up sequence.

20. The integrated circuit of claim 19, wherein the means is further configured to determine the programmable memory bank power-up sequence responsive to a plurality of configuration bits.