HIGH-ELECTRON-MOBILITY TRANSISTORS WITH COUNTER-DOPED DOPANT DIFFUSION BARRIER

• US 20180254332A1
• Filed: 09/25/2015
• Published: 09/06/2018
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mohapatra, Chandra S., Kennel, Harold W., Metz, Matthew V., Dewey, Gilbert, Rachmady, Willy, Murthy, Anand S., Kavalieros, Jack T., Ghani, Tahir
• Granted Patent: US 10,388,764 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02455 Group 13/15 materials
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A counter-doped portion of a III-V semiconductor material provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where it might otherwise behave as electrically active amphoteric contaminate in the III-V material. In some embodiments, counter-dopants (e.g., acceptor impurities) are introduced in-situ during epitaxial growth of a base portion of a sub-fin structure. With the counter-doped region limited to a base of the sub-fin structure, risk of the counter-dopant atoms thermally diffusing into an active region of a III-V transistor is mitigated.

Claims

1-21. -21. (canceled)

22. A transistor, comprising:

an active region within a fin of a first III-V semiconductor material; and

a sub-fin comprising one or more second III-V semiconductor materials, having a different III—

V alloy composition than the first III-V semiconductor material, the sub-fin between the fin and a substrate comprising silicon, wherein a first portion of the sub-fin between the substrate and a second portion of the sub-fin comprises a higher concentration of non-silicon impurities than the second portion.

23. The transistor of claim 22, wherein the first portion of the sub-fin comprises a concentration of silicon impurities that is at least an order of magnitude higher than that of the second portion.

24. The transistor of claim 22, wherein the active region comprises III-V semiconductor material that is between a pair of doped semiconductor source/drain regions;

and

further comprising;

a gate electrode disposed over the active region; and

a pair of source/drain contacts coupled to the pair of source/drain regions.

25. The transistor of claim 24, wherein:

the pair of source/drains are n-type conductivity; and

the non-silicon impurities comprise acceptor impurities.

26. The transistor of claim 25, wherein the acceptor impurities comprise at least one of C, Zn, Be, or Mg.

27. The transistor of claim 22, wherein

a concentration of the non-silicon impurities within the first portion of the sub-fin is over 1e18 atoms/cm³;

and

a concentration of the non-silicon impurities within the second portion of the sub-fin is below 1e18 atoms/cm³.

28. The transistor of claim 22, wherein:

the concentration of silicon or non-silicon impurities within the fin is below 1e18 atoms/cm³.

29. The transistor of claim 28, wherein:

the concentration of the non-silicon impurities within the first portion of the sub-fin is at least 5e18 atoms/cm³.

30. The transistor of claim 22, wherein:

the sub-fin extends to a height from an interface with the substrate; and

the first portion of the sub-fin extends from the interface to no more than 25% of the sub-fin height.

31. The transistor of claim 30, wherein:

the sub-fin extends to a height from the interface with the substrate of 200-250 nm; and

the first portion of the sub-fin extends from the interface a maximum of 20-50 nm.

32. The transistor of claim 22, wherein:

the fin structure further comprises a first III-V semiconductor material; and

the base portion and second portion of the sub-fin structure further comprise a second III-V semiconductor material,

33. The transistor of claim 32, wherein:

the first III-V semiconductor comprises a first of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP; and

at least one of the first portion and second portion of the sub-fin comprises a second of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP.

34. A device including integrated circuitry, comprising:

a plurality of n-type finFETs, each including;

an active region of a III-V semiconductor fin between a pair of doped semiconductor source/drain regions;

a sub-fin comprising one or more III-V semiconductor materials between the fin and a substrate comprising silicon, wherein a first portion of the sub-fin between the substrate and a second portion of the sub-fin comprises a higher concentration of non-silicon impurities than the second portion;

a gate electrode over the active region; and

a pair of source/drain contacts coupled to the pair of source/drain regions; and

a plurality of p-type finFETs electrically coupled to the plurality of n-type finFETs.

35. The device of claim 34, wherein the plurality of p-type finFETs each include active regions comprising a group IV semiconductor material.

36. The device of claim 34, wherein the plurality of p-type finFETs each include active regions comprising a third III-V semiconductor material disposed over a sub-fin of III-V semiconductor material substantially free of the non-silicon impurities.

37. A method of forming a transistor, the method comprising:

receiving a silicon substrate;

epitaxially growing a first thickness of a first III-V semiconductor material over a seeding surface of the substrate while supplying a non-silicon impurity to in-situ dope the first thickness;

epitaxially growing a second thickness of III-V semiconductor material over the first thickness without supplying the non-silicon impurity;

epitaxially growing a second III-V semiconductor material over the first III-V semiconductor material; and

forming an active region of the transistor in the second III-V semiconductor material.

38. The method of claim 37, further comprising:

forming a trench in a field dielectric material, the trench exposing a crystalline surface of the substrate; and

wherein;

epitaxially growing the first thickness of material further comprises growing the first III-V semiconductor material within the trench and in-situ doping the first thickness of material to a concentration of at least 5e18 non-silicon impurity atoms/cm³; and

epitaxially growing the second thickness of material further comprises growing the first III-V semiconductor material within the trench and in-situ doping the second thickness of material to a concentration of no more than 1e18 non-silicon impurity atoms/cm³.

39. The method of claim 38, wherein epitaxially growing the first thickness of material further comprises in-situ doping the first thickness of material with a source containing at least one of C, Zn, Be, or Mg.

40. The method of claim 38, wherein epitaxially growing the first and second thicknesses of material further comprises growing the first thickness to no more than 25% of a sum of the first and second thicknesses.

41. The method of claim 37, wherein:

epitaxially growing at least one of the first and second thicknesses of material further comprises growing a first of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP; and

epitaxially growing the second III-V material comprises heteroepitaxially growing a second of GaAs, GaAsSb, AlAsSb, InAs, InGaAs, InAlAs, InAlGaAs, AlGaAs, InP, GaP, AlAs, or InGaP.

42. The method of claim 37, wherein the transistor is a fin field effect transistor (finFET), and forming the transistor further comprises:

planarizing the field dielectric material with a surface of III-V semiconductor material;

recessing the field dielectric material to expose sidewalls of the III-V semiconductor material having no more than 1e18 non-silicon impurity atoms/cm³;

forming a gate stack over a channel region of the III-V semiconductor material; and

forming a pair of source/drain regions electrically coupled to opposite ends of the channel region.