FIN FIELD EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF

• US 20180261508A1
• Filed: 03/05/2018
• Published: 09/13/2018
• Est. Priority Date: 03/07/2017
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: Semiconductor Manufacturing International Corporation
• Inventors: ZHOU, Fei
• Granted Patent: US 10,460,996 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 : including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4966 : the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A fin field effect transistor (FinFET) and a method for fabricating the FinFET are provided. The method includes providing a plurality of discrete fins on a semiconductor substrate, and forming a dummy gate across a length portion of the fins and covering portions of top and sidewall surfaces of the fins. The method also includes forming an interlayer dielectric layer, covering the dummy gate and the fins, and forming an opening in the interlayer dielectric layer. In addition, the method includes forming a gate dielectric layer in the opening and on the interlayer dielectric layer, and forming a barrier layer on the gate dielectric layer. Moreover, the method includes removing the gate dielectric layer and the barrier layer from the interlayer dielectric layer, and performing an annealing treatment. Further, the method includes removing the barrier layer in the opening, and forming a metal gate in the opening.

Claims

1. A method for fabricating a fin field effect transistor (FinFET), comprising:

providing a plurality of discrete fins on a semiconductor substrate;

forming a dummy gate, across a length portion of the fins and covering portions of top and sidewall surfaces of the fins;

forming an interlayer dielectric layer, covering the dummy gate and the fins;

forming an opening in the interlayer dielectric layer by removing the dummy gate;

forming a gate dielectric layer in the opening and on the interlayer dielectric layer;

forming a barrier layer on the gate dielectric layer;

removing the gate dielectric layer and the barrier layer from the interlayer dielectric layer;

performing an annealing treatment after removing the gate dielectric layer and the barrier layer from the interlayer dielectric layer;

removing the barrier layer in the opening; and

forming a metal gate in the opening.

2. The method according to claim 1, wherein removing the barrier layer from the interlayer dielectric layer includes:

filling the opening with an organic coating layer;

removing the barrier layer exposed by the organic coating layer; and

removing the organic coating layer.

3. The method according to claim 2, wherein filling the opening with the organic coating layer includes:

forming an organic coating film to cover the barrier layer; and

back-etching the organic coating film over the interlayer dielectric layer to form the organic coating layer in the opening.

4. The method according to claim 2, wherein:

removing the barrier layer exposed by the organic coating layer includes a dry etching process using parameters including;

an etching gas including SiH₄,

a SiH₄ gas flow rate in a range of approximately 30 sccm-3000 sccm,

a temperature in a range of approximately 360°

C.-520°

C., and

a pressure in a range of approximately 0.03 torr-10 torr.

5. The method according to claim 2, wherein:

removing the organic coating layer includes a dry etching process using parameters including;

etching gases including one or more of N₂ and H₂,

a N₂ gas flow rate in a range of approximately 1000 sccm-8000 sccm,

a H₂ gas flow rate in a range of approximately 500 sccm-2000 sccm,

a temperature in a range of approximately 150°

C.-350°

C., and

a pressure in a range of approximately 500 mtorr-2000 mtorr.

6. The method according to claim 1, wherein:

forming the gate dielectric layer includes an atomic layer deposition process using parameters including;

a precursor including Si,

a temperature in a range of approximately 80°

C.-300°

C.,

a pressure in a range of approximately 5 torr-20 torr, and

a repeated deposition for approximately 5 times-50 times.

7. The method according to claim 1, further including:

forming an interface dielectric layer on a bottom of the opening, before forming the gate dielectric layer, such that the interface dielectric layer is formed between the semiconductor substrate and the gate dielectric layer.

8. The method according to claim 7, wherein:

the interface dielectric layer is formed by an oxidation process using parameters including;

an introduced gas including H₂O₂ gas, and

a reaction time in a range of approximately 5 seconds-500 seconds at a temperature in a range of approximately 10°

C.-100°

C., or

introduced gases including H₂ and O₂,

a H₂ gas flow rate in a range of approximately 0.2 slm-10 slm,

an O₂ gas flow rate in a range of approximately 10 slm-100 slm,

a reaction temperature in a range of 800°

C.-1100°

C.,

a pressure in a range of approximately 4 torr-100 torr, and

time in a range of approximately 5 seconds-30 seconds.

9. The method according to claim 7, wherein:

the interface dielectric layer is made of a material including one of silicon oxide and silicon oxynitride; and

a thickness of the interface dielectric layer is in a range of approximately 5 Å

-10 Å

.

10. The method according to claim 1, wherein:

a thickness of the barrier layer is in a range of approximately 20 Å

-50 Å

.

11. The method according to claim 1, wherein:

the annealing treatment includes a spike annealing process or a rapid annealing process, wherein;

the spike annealing process is performed at a temperature in a range of approximately 900°

C.-1050°

C., and

the rapid annealing process is performed at a temperature in a range of approximately 900°

C.-1050°

C. for an annealing time in a range of approximately 5 seconds-20 seconds.

12. The method according to claim 1, further including:

forming a first working function layer on the gate dielectric layer after forming the gate dielectric layer and before forming the barrier layer; and

removing the first working function layer on the interlayer dielectric layer, while removing the gate dielectric layer and the barrier layer from the interlayer dielectric layer.

13. The method according to claim 12, wherein:

the first working function layer is made of a material including one of titanium nitride and tantalum nitride.

14. The method according to claim 1, wherein:

the gate dielectric layer is made of a material including one of hafnium oxide and lanthanum hafnium oxide.

15. The method according to claim 1, wherein:

the barrier layer is made of a material including silicon.

16. The method according to claim 1, further including:

forming a second working function layer in the opening after removing the barrier layer in the opening and before forming the metal gate, and

forming the metal gate on the second working function layer.

17. The method according to claim 1, after forming the dummy gate and before forming the interlayer dielectric layer, further including:

forming a sidewall spacer on sidewalls of the dummy gate, and

forming source and drain doped regions in the fins on both sides of the dummy gate and the sidewall spacer.

18. A FinFET, comprising:

a semiconductor substrate;

a plurality of discrete fins on the semiconductor substrate;

an interlayer dielectric layer on the semiconductor substrate and on the fins, wherein the interlayer dielectric layer contains an opening;

a gate dielectric layer on the fins;

a barrier layer on the gate dielectric layer, wherein the barrier layer is made of a material including silicon;

a metal gate on the barrier layer;

an opening in the interlayer dielectric layer, wherein the barrier layer surrounds the opening; and

source and drain doped regions in the fins.

19. The FinFET according to claim 18, further including:

an interface dielectric layer on the fins;

the gate dielectric layer on the interface dielectric layer;

a first working function layer on the gate dielectric layer; and

the barrier layer on the first working function layer.

20. The FinFET according to claim 18, wherein:

a thickness of the barrier layer is in a range of approximately 20 Å

-50 Å

.