TONE INVERSION METHOD AND STRUCTURE FOR SELECTIVE CONTACT VIA PATTERNING
First Claim
1. A method for tone inversion for integrated circuit fabrication, the method comprising:
- forming a plurality of gate stacks over a semiconductor substrate;
forming a spacer layer over sidewalls of the gate stacks;
forming a dielectric layer over the spacer layers and between adjacent gate stacks;
forming a patterning structure over the gate stacks, the spacer layers and the dielectric layer, the patterning structure comprising, from bottom to top, an etch stop layer, an amorphous carbon layer, an adhesion layer, an amorphous silicon layer, an optional oxide layer, and a hard mask layer;
etching the hard mask layer, the optional oxide layer and the amorphous silicon layer to form a first pattern in the amorphous silicon layer;
forming a layer of image reverse material over the adhesion layer and laterally adjacent to the first pattern in the amorphous silicon layer, wherein the layer of image reverse material defines a second pattern complementary to the first pattern;
removing the amorphous silicon layer; and
using the image reverse material layer as a mask, etching the first pattern into the dielectric layer.
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Abstract
A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.
16 Citations
17 Claims
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1. A method for tone inversion for integrated circuit fabrication, the method comprising:
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forming a plurality of gate stacks over a semiconductor substrate; forming a spacer layer over sidewalls of the gate stacks; forming a dielectric layer over the spacer layers and between adjacent gate stacks; forming a patterning structure over the gate stacks, the spacer layers and the dielectric layer, the patterning structure comprising, from bottom to top, an etch stop layer, an amorphous carbon layer, an adhesion layer, an amorphous silicon layer, an optional oxide layer, and a hard mask layer; etching the hard mask layer, the optional oxide layer and the amorphous silicon layer to form a first pattern in the amorphous silicon layer; forming a layer of image reverse material over the adhesion layer and laterally adjacent to the first pattern in the amorphous silicon layer, wherein the layer of image reverse material defines a second pattern complementary to the first pattern; removing the amorphous silicon layer; and using the image reverse material layer as a mask, etching the first pattern into the dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A structure for tone inversion for integrated circuit fabrication, comprising:
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a semiconductor substrate; and a patterning structure disposed over the semiconductor substrate, the patterning structure comprising, from bottom to top, an etch stop layer, an amorphous carbon layer, an adhesion layer, an amorphous silicon layer, an optional oxide layer, and a hard mask layer. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification