FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS

• US 20180261513A1
• Filed: 05/10/2018
• Published: 09/13/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo
• Granted Patent: US 10,262,901 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0603 characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions isolation regions between components H01L21/76; design considerations for integrated circuits H01L27/00; geometrical design considerations for devices H01L29/0657
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET

Abstract

A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Claims

1. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:

forming a dummy fin trench in a substrate;

forming a dummy fin fill in the dummy fin trench;

forming a first array of vertical fins on a first side of the dummy fin fill, a second array of vertical fins on a second side of the dummy fin fill, and one or more dummy fins from the dummy fin fill between the first array of vertical fins and second array of vertical fins; and

removing the one or more dummy fins to form a gap between the neighboring arrays of vertical fins.

2. The method of claim 1, wherein a depth of the dummy fin trench is greater than the height of the vertical fins in the first array and the second array.

3. The method of claim 1, wherein the width of the dummy fin trench is sufficient to form two columns of dummy fins.

4. The method of claim 1, wherein the dummy fin fill and the one or more dummy fins are made of amorphous silicon (a-Si), poly-crystalline silicon (p-Si), amorphous silicon-germanium (a-SiGe), or poly-crystalline silicon-germanium (p-SiGe).

5. The method of claim 4, wherein the vertical fins are single crystal silicon, and the one or more dummy fins are removed by a selective HCl etch.

6. The method of claim 1, wherein the first array of vertical fins is an N column by M row arrangement of vertical fins, and the second array of vertical fins is an X column by Y row arrangement of vertical fins, where X is different than N and Y is different from M.

7. The method of claim 6, wherein the one or more dummy fins are located the same pitch distance from an adjacent vertical fin, as the pitch between adjacent vertical fins in the first array.

8. The method of claim 7, further comprising forming a first doped region in the substrate below the first array of vertical fins, and a second doped region in the substrate below the second array of vertical fins.

9. The method of claim 8, further comprising forming a punch-through stop in a lower portion of the vertical fins in the first array.

10. The method of claim 9, further comprising forming a top source/drain on the vertical fins in the first array.

11. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:

forming a dummy fin trench in a substrate;

forming a dummy fin fill in the dummy fin trench;

forming a first array of vertical fins on a first side of the dummy fin fill, wherein the first array of vertical fins is an N column by M row pattern;

forming a second array of vertical fins on a second side of the dummy fin fill, wherein the second array of vertical fins is an X column by Y row pattern;

forming M dummy fins from the dummy fin fill between the first array of vertical fins and second array of vertical fins; and

removing the M dummy fins to form a gap between the neighboring arrays of vertical fins.

12. The method of claim 11, wherein the depth of the dummy fin trench is in a range of about 20 nm to about 200 nm.

13. The method of claim 12, wherein the width of the dummy fin trench is in a range of about 30 nm to about 300 nm.

14. The method of claim 13, wherein the dummy fin trench forms a form step with a ledge adjacent to the M vertical fins adjacent to the M dummy fins.

15. The method of claim 14, wherein the step has a height in the range of about 5 nm to about 50 nm.

16. The method of claim 15, wherein the dummy fin fill and the dummy fins are made of amorphous silicon (a-Si), poly-crystalline silicon (p-Si), amorphous silicon-germanium (a-SiGe), or poly-crystalline silicon-germanium (p-SiGe).

17. A method of forming arrays of fin field effect transistors (finFETs) having fin(s) with reduced dimensional variations, comprising:

forming a dummy fin trench in a substrate;

forming a dummy fin fill in the dummy fin trench;

forming a first array of vertical fins on a first side of the dummy fin fill, wherein the first array of vertical fins is an N column by M row pattern;

forming a second array of vertical fins on a second side of the dummy fin fill, wherein the second array of vertical fins is an X column by Y row pattern;

forming M dummy fins from the dummy fin fill between the first array of vertical fins and second array of vertical fins;

forming a first doped region in the substrate below the first array of vertical fins;

forming a second doped region in the substrate below the second array of vertical fins; and

removing the M dummy fins to form a gap between the neighboring arrays of vertical fins.

18. The method of claim 17, wherein the vertical fins of the first array are electrically coupled to the first doped region.

19. The method of claim 18, further comprising forming a top source/drain on each of the vertical fins in the first array.

20. The method of claim 19, further comprising forming a gate structure on the vertical fins in the first array to form a multi-fin vertical field effect transistor.