VERTICAL POWER MOS-GATED DEVICE WITH HIGH DOPANT CONCENTRATION N-WELL BELOW P-WELL AND WITH FLOATING P-ISLANDS

• US 20180261666A1
• Filed: 02/12/2018
• Published: 09/13/2018
• Est. Priority Date: 03/09/2017
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N., Du, Wenfang, Blanchard, Richard A., Pu, Kui, Su, Shih-Tzung
• Granted Patent: US 10,157,983 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a power MOSFET or IGBT cell includes an N-type drift region grown over the substrate. An N-type layer, having a higher dopant concentration than the drift region, is then formed over the drift region. A P-well is formed over the N-type layer, and an N+ source/emitter region is formed in the P-well. A gate is formed over the P-well'"'"'s lateral channel and has a vertical extension into a trench. A positive gate voltage inverts the lateral channel and increases the vertical conduction in the N-type layer along the sidewalls of the trench to reduce on-resistance. A vertical shield field plate is also in the trench and may be connected to the gate. The field plate laterally depletes the N-type layer when the device is off to increase the breakdown voltage. Floating P-islands in the N-type drift region increase breakdown voltage and reduce the saturation current.

Claims

1. A vertical transistor comprising a semiconductor substrate having a first electrode on its bottom surface;

a first layer of a first conductivity type overlying the substrate, the first layer having a first dopant concentration;

a first region of the first conductivity type overlying the first layer, the first region layer having a second dopant concentration higher than the first dopant concentration, the first region having a top surface;

a trench having a vertical sidewall adjoining the first region , the trench containing a conductor insulated from the first layer and first region;

a second region of a second conductivity type overlying the top surface of the first region, the second region having a top surface;

a third region of the first conductivity type overlying the top surface of the second region, wherein an area between the third region and an edge of the second region comprises a channel for inversion by a gate;

a conductive gate insulated from and proximate to the channel for creating a conductive path in the channel when the gate is biased above a threshold voltage, the gate also being insulated from and proximate to the first region for increasing a carrier concentration in the first region along a vertical section of the first region when the gate is biased to turn the transistor on so as to form a vertical low-conductivity path through the first region; and

a second electrode electrically contacting the second region and the third region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a current flows between the first electrode and the second electrode.

2. The transistor of claim 1 wherein the substrate is of the first conductivity type and the transistor is a MOSFET.

3. The transistor of claim 1 wherein the substrate is of the second conductivity type and the transistor is an insulated gate bipolar transistor (IGBT).

4. The transistor of claim 1 wherein the channel is a lateral channel below a first portion of the gate, wherein the gate has a vertical extension that faces a side of the first region.

5. The transistor of claim 1 wherein the channel is a vertical channel and the gate is formed in the trench.

6. The transistor of claim 1 further comprising a vertical field plate in the trench facing a vertical sidewall of the first layer and insulated from the sidewall.

7. The transistor of claim 6 wherein the vertical field plate is electrically connected to the second electrode.

8. The transistor of claim 6 wherein the vertical field plate is electrically connected to the gate.

9. The transistor of claim 1 wherein the trench is along at least a portion of the first layer and the first region, the trench containing a conductive material, the transistor further comprising:

a doped shield region of the second conductivity type below the trench and contacting the first layer.

10. The transistor of claim 1 wherein the first region is formed as a well region surrounding the second region.

11. The transistor of claim 1 wherein the first region is formed as an epitaxial layer below the second region.

12. The transistor of claim 1 wherein the first region has a dopant concentration that is at least 1.5 times that of the first layer.

13. The transistor of claim 1 further comprising one or more floating fourth regions of the second conductivity type formed in the first layer.

14. A vertical transistor comprising

a semiconductor substrate having a first electrode on its bottom surface;

a first layer of a first conductivity type overlying the substrate;

a trench having a vertical sidewall, the trench containing a conductor insulated from the first layer;

a first region of a second conductivity type overlying the first layer, the first region having a top surface;

a second region of the first conductivity type overlying the top surface of the first region, wherein an area between the second region and an edge of the first region comprises a channel for inversion by a gate;

a conductive gate insulated from and proximate to the channel for creating a conductive path in the channel when the gate is biased above a threshold voltage;

at least one third region of the second conductivity type formed completely within the first layer, the at least one third region electrically floating; and

a second electrode electrically contacting the first region and the second region, wherein when a voltage is applied between the first electrode and the second electrode and the gate is biased above the threshold voltage, a current flows between the first electrode and the second electrode.

15. The transistor of claim 14 wherein the at least one third region comprises a plurality of third regions.

16. The transistor of claim 14 wherein the trench is along at least a portion of the first layer, the trench containing a conductive material, the transistor further comprising:

a doped shield region of the second conductivity type below the trench and contacting the first layer.

17. The transistor of claim 14 wherein the substrate is of the first conductivity type and the transistor is a MOSFET.

18. The transistor of claim 14 wherein the substrate is of the second conductivity type and the transistor is an insulated gate bipolar transistor (IGBT).

19. The transistor of claim 14 wherein the channel is a lateral channel below a first portion of the gate, wherein the gate has a vertical extension that faces a side of the first region.

20. The transistor of claim 14 wherein the channel is a vertical channel and the gate is formed in the trench.