SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

• US 20180265347A1
• Filed: 03/14/2018
• Published: 09/20/2018
• Est. Priority Date: 03/16/2017
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: LEE, Ming Yen, SUNG, Chia Hao, HUANG, Ching-Han, TSAI, Yu-Hsuan
• Granted Patent: US 10,689,248 B2
• Time in Patent Office: Days
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/07 Interconnects
• CPC Class Codes: B81B 3/007 For controlling stiffness, e.g. ribs
• CPC Class Codes: B81B 7/0061 suitable for fluid transfer from the MEMS out of the package or vice versa, e.g. transfer of liquid, gas, sound
• CPC Class Codes: B81C 1/00658 Treatments for improving the stiffness of a vibrating element
• CPC Class Codes: B81C 2201/0156 Lithographic techniques
• CPC Class Codes: B81C 2203/032 Gluing
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/12 Mountings, e.g. non-detachable insulating substrates
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/31 characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Abstract

The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.

Claims

1. A semiconductor device package, comprising:

a substrate;

a support structure disposed on the substrate;

an electronic component disposed on the support structure; and

an adhesive disposed between the substrate and the electronic component and covering the support structure,

wherein a hardness of the support structure is less than a hardness of the electronic component.

2. The semiconductor device package of claim 1, wherein the support structure includes polymeric materials.

3. The semiconductor device package of claim 1, wherein the support structure includes photosensitive materials.

4. The semiconductor device package of claim 1, wherein the support structure is a solder mask.

5. The semiconductor device package of claim 1, wherein the electronic component is a microelectromechanical systems (MEMS) device.

6. The semiconductor device package of claim 1, wherein the MEMS device includes a membrane.

7. A semiconductor device package, comprising:

a substrate having an opening penetrating the substrate;

a support structure disposed on the substrate;

a MEMS device disposed on the support structure, the MEMS device having a cavity corresponding to the opening of the substrate; and

an adhesive disposed between the substrate and the MEMS device and covering the support structure,

wherein a hardness of the support structure is less than a hardness of the MEMS device.

8. The semiconductor device package of claim 7, wherein the support structure includes polymeric materials.

9. The semiconductor device package of claim 7, wherein the support structure includes photosensitive materials.

10. The semiconductor device package of claim 7, wherein the support structure is a solder mask.

11. The semiconductor device package of claim 7, wherein the MEMS device includes a membrane.

12. The semiconductor device package of claim 7, further comprising a dam-like structure disposed between the substrate and the MEMS device and surrounding the opening of the substrate.

13. The semiconductor device package of claim 12, wherein the dam-like structure and the support structure are formed of the same material.

14. The semiconductor device package of claim 13, wherein the dam-like structure and the support structure are solder masks.

15. A method of manufacturing a semiconductor device package, the method comprising:

(a) providing a substrate;

(b) placing a photosensitive layer on the substrate;

(c) removing a portion of the photosensitive layer to form a support structure;

(d) applying an adhesive to cover the support structure; and

(e) connecting an electronic component on the support structure through the adhesive.

16. The method of claim 15, wherein operation (c) further comprising:

exposing the photosensitive layer to form a pattern defining the support structure; and

removing the portion of the photosensitive layer to remain the pattern.

17. The method of claim 15, wherein operation (c) further comprises:

forming an opening to penetrate the substrate, and wherein in operation (e), the electronic component has a cavity corresponding to the opening of the substrate.

18. The method of claim 17, before operation (d), further comprising forming a dam-like structure surrounding the opening of the substrate.

19. The method of claim 18, wherein the dam-like structure is formed by:

exposing the photosensitive layer to form a pattern defining the dam-like structure; and

removing the portion of the photosensitive layer to remain the pattern.

20. The method of claim 15, further comprising curing the adhesive to connect the electronic component to the support structure.