MEMORY SYSTEM

• US 20180267895A1
• Filed: 10/19/2017
• Published: 09/20/2018
• Est. Priority Date: 03/17/2017
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: JUNG, Byung-Soo
• Granted Patent: US 10,671,523 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.

Claims

1. A memory system, comprising:

plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks;

a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks;

a first access controller suitable for controlling an access to the first memory blocks;

a second access controller suitable controlling an access to the second memory blocks; and

a bad block controller suitable for;

selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each, of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and

transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.

2. The memory system of claim 1, wherein the bad block controller includes:

a first bad block table including mapping relation information between partial entries of the bad physical addresses with first substitute physical addresses corresponding to the first memory blocks;

a second bad block table including mapping relation information between remaining partial entries of the bad physical addresses with second substitute physical addresses corresponding to the second memory blocks; and

a path control element suitable for;

selecting the first access controller and transferring the first substitute physical addresses when the first and second physical addresses are identical to the partial entries of the bad physical addresses;

selecting the second access controller and transferring the second substitute physical addresses when the first and second physical addresses are identical to the remaining partial entries of the bad physical addresses; and

selecting the first access controller and transferring the first physical addresses or selecting the second access controller and transferring the second physical addresses when the first and second physical addresses are not identical to the bad physical addresses.

3. The memory system of claim 2, wherein the path control element includes:

a first specific path control element suitable for;

selecting the first access controller and transferring the first substitute physical addresses when the first physical address is identical to the partial entries of the bad physical addresses,

selecting the second access controller and transferring the second substitute physical addresses when the first physical address is identical to the remaining partial entries of the bad physical addresses, and

selecting the first access controller and transferring the first physical addresses when the first physical addresses is not identical to the bad physical addresses; and

a second specific path control element suitable for;

selecting the second access controller and transferring the second substitute physical addresses when the second physical address is identical to the remaining partial entries of the bad physical addresses,

selecting the first access controller and transferring the first substitute physical addresses when the second physical address identical to the partial entries of the bad physical addresses, and

selecting the second access controller and transferring the second physical addresses when the second physical addresses is not identical to the bad physical addresses.

4. The memory system of claim 2, wherein the bad block controller further includes a bad information loading element suitable for:

loading information of the bad physical addresses and the substitute physical addresses from the first and second memory devices,

deciding which substitute physical addresses are to be mapped to the bad physical addresses based on the number of the loaded bad physical addresses, and

generating the first and second bad block tables.

5. The memory system of claim 4, wherein the bad information loading element generates the first and second bad block tables by checking out the total number of the bad physical addresses that are stored in the first and second memory devices, and distributes the bad physical addresses in such a manner that the number of the partial entries of the bad physical addresses and the number of the remaining partial entries of the bad physical addresses do not exceed a predetermined number of difference.

6. A memory system, comprising:

a plurality of first memory devices each coupled to a first way of a first channel and including a plurality of first memory blocks;

a plurality of second memory devices each coupled to a second way of the first channel and including a plurality of second memory blocks;

a plurality of third memory devices each coupled to a first way of a second channel and including a plurality of third memory blocks;

a plurality of fourth memory devices each coupled to a second way of the second channel and including a plurality of fourth memory blocks;

a first access controller suitable for controlling an access to the first memory blocks;

a second access controller suitable for controlling an access to the second memory blocks;

a third access controller suitable for controlling an access to the third memory blocks;

a fourth access controller suitable for controlling an access to the fourth memory blocks;

a first channel controller suitable for controlling an access to the first and second access controllers;

a second channel controller suitable for controlling an access to the third and fourth access controllers;

a first bad block controller suitable for;

selecting one between the first and second access controllers by comparing first channel bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with the first and second physical addresses respectively corresponding to the first and second memory blocks, and

transferring one of the first and second physical addresses and substitute physical addresses that replace the first channel bad physical addresses; and

a second bad block controller suitable for;

selecting one between the third and fourth access controllers by comparing second channel bad physical addresses corresponding to bad blocks included in each of the third and fourth memory devices with the third and fourth physical addresses respectively corresponding to the third and fourth memory blocks, and

transferring one of the third and fourth physical addresses and substitute physical addresses that replace the second channel bad physical addresses.

7. The memory system of claim 6, wherein the first bad block controller includes:

a first bad block table including mapping relation information between partial entries of the first bad physical addresses with first substitute physical addresses corresponding to the first memory blocks;

second bad block table including mapping, relation information between partial entries of the second bad physical addresses with second substitute physical addresses corresponding to the second memory blocks; and

a first path control element suitable for;

selecting the first channel controller and the first access controller and transferring he first substitute physical addresses when the first and second physic addresses are identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical addresses when the first and second physical addresses are identical to the second bad physical addresses, and

selecting the, first channel controller and the first access controller and transferring the first physical addresses or selecting the first channel controller and the second access controller and transferring the second physical addresses when the first arid second physical addresses are not identical to the first channel bad physical addresses.

8. The memory system of claim 7, wherein the second bad block controller includes:

a third bad block table including mapping relation information between partial entries of the third bad physical addresses with third substitute physical addresses corresponding to the third memory blocks;

a fourth bad block table including mapping relation information between partial entries of the fourth bad physical addresses with fourth substitute physical addresses corresponding to the fourth memory blocks; and

a second path control element suitable for;

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the third physical addresses and the fourth physical addresses are identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the third and fourth physical addresses are identical to the fourth bad physical addresses, and

selecting the second channel controller and the third access controller and transferring the third physical addresses or selecting the second channel controller and the fourth access controller and transferring the fourth physical addresses when the third and fourth physical addresses are not identical to the second channel bad physical addresses.

9. The memory system of claim 8, wherein the first path control element includes:

a first specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical addresses when the first physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical addresses when the first physical address is identical to the second bad physical addresses, and

selecting the first channel controller and the first access controller and transferring the first physical addresses when the first physical address is not identical to the first channel bad physical addresses; and

a second specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical addresses when the second physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical addresses when the second physical address is identical to the second bad physical ad dresses, and

selecting the first channel controller and the second access controller and transferring the second physical addresses when the second physical address is not identical to the first channel bad physical addresses.

10. The memory system of claim 9, wherein the second path control element includes:

a third specific path control element suitable for;

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the third physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the third physical address is identical to the fourth bad physical addresses, and

selecting the second channel controller and the third access controller and transferring the third physical addresses when the third physical addresses are not identical to the second channel bad physical addresses; and

a fourth specific path control element suitable for;

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the fourth physical address is identical to the third bad physical addresses;

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the fourth physical address is identical to the fourth bad physical addresses; and

selecting the second channel controller and the fourth access controller and transferring the fourth physical addresses when the fourth physical address is not identical to the second channel bad physical addresses.

11. The memory system of claim 8, wherein the first bad block controller further includes a first bad information loading element suitable for:

loading information of the first channel bad physical addresses and the first and second substitute physical addresses from the first and second memory devices,

deciding which of the and second substitute physical addresses are to be mapped to the first channel bad physical addresses based on the number of the loaded first channel bad physical addresses, and

generating the first and second bad block tables.

12. The memory system of claim 11, wherein the first bad information loading element generates the first and second bad block tables by checking out the total number of the first channel bad physical addresses that are stored in the first and second memory devices, and distributes the first channel bad physical addresses in such a manner that the number of the first bad physical addresses and the number of the second bad physical addresses do not exceed a predetermined number of difference.

13. The memory system of claim 8, wherein the second bad block controller further includes a second bad information loading element suitable for:

loading information of the second channel bad physical addresses and the third and fourth substitute physical addresses that are stored in the third and fourth memory devices,

deciding which of the third and fourth substitute physical addresses are to be mapped to the second channel bad physical addresses based on the number of the loaded second channel bad physical addresses, and

generating the third and fourth bad block tables.

14. The memory system of claim 13, wherein the second had information loading element generates the third and fourth bad block tables by checking out the total num tier of the second channel bad physical addresses that are stored in the third and fourth memory devices, and distributes the second channel bad physical addresses in such a manner that the number of the third bad physical addresses and the number of the fourth bad physical addresses do not exceed a predetermined number of difference.

15. A memory system, comprising:

a plurality of first memory devices each coupled to a first way of a first channel and including a plurality of first memory blocks;

a plurality of second memory devices each coupled to a second way of the first channel and including a plurality of second memory blocks;

a plurality of third memory devices each coupled to a first way of a second channel and including a plurality of third memory blocks;

a plurality of fourth memory devices each coupled to a second way of the second channel and including a plurality of fourth memory blocks;

a first access controller suitable for controlling an access to the first memory blocks;

a second access controller suitable for controlling an access to the second memory blocks;

a third access controller suitable for controlling an access to the third memory blocks;

a fourth access controller suitable for controlling an access to the fourth memory blocks;

a first channel controller suitable for controlling an access to the first and second access controllers;

a second channel controller suitable for controlling an access to the third and fourth access controllers;

a bad block controller suitable for;

selecting one between the first and second channel controllers and then selecting one among the first to fourth second way controllers related to the selected one between the first and second controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first to fourth memory devices with the first to fourth physical addresses, and

transferring one of the first to fourth physical addresses and substitute physical addresses that replace the bad physical addresses.

16. The memory system of claim 15, wherein the bad block controller includes:

a first bad block table including mapping relation information between partial entries of the first bad physical addresses with first substitute physical addresses corresponding to the first memory blocks;

second bad block table including mapping relation information between partial entries of the second bad physical addresses with second substitute physical addresses corresponding to the second memory blocks;

a third bad block table including mapping relation information between partial entries of the third bad physical addresses with third substitute physical addresses corresponding to the third memory blocks;

a fourth bad block table including mapping relation information between partial entries of the fourth bad physical addresses with fourth substitute physical addresses corresponding to the fourth memory blocks; and

a path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical addresses when the first to fourth physical addresses are identical to the first bad physical addresses;

selecting the firs channel controller and the second access controller and transferring the second substitute physical addresses when the first to fourth physical addresses are identical to the second bad physical addresses;

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the first to fourth physical addresses are identical to the third bad physical addresses;

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the first to fourth physical addresses are identical to the fourth bad physical addresses; and

selecting the, first channel controller and the first access controller and transferring the first physical addresses or selecting the first channel controller and the second access controller and transferring the second physical addresses or selecting the second channel controller and the third access controller and transferring the third physical addresses, or selecting the second channel controller and the fourth access controller and transferring the fourth physical addresses when the first to fourth physical addresses are not identical to the bad physical addresses.

17. The memory system of claim 16, wherein the path control element includes:

a first specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical addresses when the first physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical addresses when the first physical address is identical to the second bad physical addresses,

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the first physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the first physical address s identical to the fourth bad physical addresses, and

selecting the first channel controller and the first access controller and transferring the first physical addresses when the first physical address is not identical to the bad physical addresses;

a second specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical addresses when the second physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical addresses when the second physical address is identical to the second bad physical addresses,

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the second physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the second physical address is identical to the fourth bad physical addresses, and

selecting the first channel controller and the second access controller and transferring the second physical addresses when the second physical, address is not identical to the bad physical addresses;

a third specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical addresses when the third physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical addresses when the third physical address is identical to the second bad physical addresses,

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the third physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the third physical address is identical to the fourth bad physical addresses, and

selecting the second channel controller and the third access controller and transferring the third physical addresses when the third physical address is not identical to the bad physical addresses; and

a fourth specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical addresses when the fourth physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical addresses when the fourth physical address is identical to the second bad physical addresses,

selecting the second channel controller and the third access controller and transferring the third substitute physical addresses when the fourth physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical addresses when the fourth physical address is identical to the fourth bad physical addresses, and

selecting the second channel controller and the fourth access controller and transferring the fourth physical addresses when the fourth physical ad dress is not identical to the bad physical addresses.

18. The memory system of claim 16, wherein the bad block controller further includes a bad information loading element suitable for:

loading information of the bad physical addresses and the first to fourth substitute physical addresses from the first to fourth memory devices,

deciding which of the first to fourth substitute physical addresses are to be mapped to the bad physical addresses based on the number of the loaded bad physical addresses, and

generating the first to fourth bad block tables.

19. The memory system claim 18, wherein the bad information loading element generates the first to fourth bad block tables by checking out the total number of the bad physical addresses that are stored in the first to fourth memory devices, and distributes the bad physical addresses in such a manner that the number of the first bad physical addresses, the number of the second bad physical addresses the number of the third bad physical addresses, and the number of the fourth bad physical addresses do not exceed a predetermined number of difference.