SIGNAL PROCESSING APPARATUS

• US 20180268794A1
• Filed: 01/22/2018
• Published: 09/20/2018
• Est. Priority Date: 03/15/2017
• Status: Active Grant

• Current Assignee: Casio Computer Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: YOKOTA, Masuo
• Granted Patent: US 10,339,907 B2
• Time in Patent Office: Days
• CPC Class Codes: G10H 1/043 Continuous modulation
• CPC Class Codes: G10H 1/125 using a digital filter
• CPC Class Codes: G10H 2210/281 Reverberation or echo
• CPC Class Codes: G10H 2250/115 FIR impulse, e.g. for echoes or room acoustics, the shape of the impulse response is specified in particular according to delay times FIR filters for musical processing G10H2250/075
• CPC Class Codes: G10H 2250/145 Convolution, e.g. of a music input signal with a desired impulse response to compute an output transforms, i.e. mathematical transforms into domains appropriate for musical signal processing, coding or compression G10H2250/215
• CPC Class Codes: H03H 17/0213 Frequency domain filters using Fourier transforms
• CPC Class Codes: H03H 17/06 Non-recursive filters

Abstract

A signal processing apparatus has a first memory in which plural pieces of FIR coefficient data used for implementing an FIR filter algorithm are stored, a second memory which stores plural pieces of input data to be subjected to the FIR filter algorithm, and a processor implements the FIR filter algorithm using the plural pieces of FIR coefficient data stored in the first memory and the plural pieces of input data stored in the second memory as many times as the number corresponding to a designated filter order, in which filter algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up. The signal processing apparatus is provided, which can implement plural sorts of FIR filter algorithms of filter order which can be changed flexibly.

Claims

1. A signal processing apparatus comprising:

a first memory in which plural pieces of coefficient data used for implementing a filter algorithm are stored; and

a processor which receives plural pieces of input data to be subjected to the filter algorithm, executes the filter algorithm using the plural pieces of coefficient data stored in the first memory and the plural pieces of received input data as many times as the number corresponding to a designated filter order, and outputs an execution result of the filter algorithm, in which filter algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up.

2. The signal processing apparatus according to claim 1, further comprising:

a second memory which stores the plural pieces of received input data, wherein

the filter algorithm is a Finite Impulse Response (FIR) filter algorithm;

the first memory stores plural pieces of FIR coefficient data; and

the processor implements the FIR filter algorithm using the plural pieces of FIR coefficient data stored in the first memory and the plural pieces of received input data stored in the second memory as many times as the number corresponding to a designated filter order, in which filter algorithm each piece of FIR coefficient data and each piece of input data are multiplied together and resultant products are summed up.

3. The signal processing apparatus according to claim 1, wherein

the processor can designate a number corresponding to the filter order of the filter algorithm to be implemented within a predetermined number;

the first memory stores at least the predetermined number of pieces of coefficient data; and

the second memory stores at least the predetermined number of pieces of input data.

4. The signal processing apparatus according to claim 1, further comprising:

a filter algorithm implementing unit which implements a first-order filter algorithm, wherein

the first memory stores plural coefficient data sets as many as the number corresponding to the filter order of the filter algorithm at least for one sort of filter algorithm of variable filter order;

the second memory stores input data set from the last sample to the sample before the (filter order−

1)-th sample for the filter algorithm as delay data set; and

the processor successively supplies the coefficient data stored in the first memory and current input data or the delay data stored in the second memory to the filter algorithm implementing unit for each filter algorithm, and makes the filter algorithm implementing unit repeatedly implement the first-order filter algorithm by time division processing of a dividing time length corresponding to the filter order and output output-data within each sampling period.

5. The signal processing apparatus according to claim 4, wherein the processor

assigns continuous time durations of a time length counted by a clock having a cycle subdividing a sampling period to the filter algorithms respectively, each time length being long enough for implementing the filter algorithm of the filter order in the sampling period,

successively supplies the coefficient data stored in the first memory and the current input data or the delay data stored in the second memory to the filter algorithm implementing unit, and makes the filter algorithm implementing unit implement the filter algorithm in the continuous time duration, in which filter algorithm the successively supplied data are multiplied together and resultant products are summed up in synchronism with the clock, and

controls the filter algorithm implementing unit to output output-data of the filter algorithms in each sampling period.

6. The signal processing apparatus according to claim 4, wherein the filter algorithm implementing unit comprises:

a first register which retains in synchronism with the clock the coefficient data output from the first memory;

a first selector which selects either one of input data in the current sampling period and the delay data output from the second memory;

a second register which retains in synchronism with the clock the data output from the first selector;

a multiplier which multiplies the coefficient data output from the first register and the data output from the second register to obtain product data;

a third register which retains in synchronism with the clock the product data output from the multiplier;

an adder which adds the product data output from the third register and current summed-up data together to obtain sum data;

a fourth register which retains in synchronism with the clock the sum data output from the adder; and

a second selector which selects either one of data of a value “

0” and

the sum data output from the fourth register to feed back the selected data as the summed-up data to the adder.

7. An effect applying apparatus for applying an acoustic effect to an original tone by convoluting the original tone with impulse response data of an acoustic effect tone, the apparatus comprising:

a time-domain convolution implementing unit which employs the FIR filter algorithm implemented by the signal processing apparatus recited in claim 2 to convolute the original tone with the first half data of the impulse response data in the time domain of unit of the sampling period; and

a frequency-domain convolution implementing unit which implement a Fast Fourier Transform algorithm on second half data of the impulse response data in the frequency domain of unit of block, thereby convoluting the original tone with the second half data.

8. The effect applying apparatus according to claim 7, wherein

the first half data and the second half data of the impulse response data are set arbitrarily.

9. The effect applying apparatus according to claim 7, further comprising:

a setting unit which decides a block size of the block and sets a filter order of the FIR filter algorithm and an FFT point number of FFT algorithm implementing unit to twice as large as the block size.

10. The effect applying apparatus according to claim 9, wherein

the setting unit decides the block size in accordance with a time length of the impulse response data.

11. The effect applying apparatus according to claim 9, wherein

the setting unit decides the block size in accordance with a tone generation setting condition of the original tone.

12. The effect applying apparatus according to claim 9, wherein the setting unit

stores coefficient data in the time domain of the impulse response data;

after deciding the block size, removes FIR coefficient data of filter order equivalent to twice as large as the block size to be used for implementing the FIR filter algorithm from the coefficient data of the impulse response data to obtain remaining coefficient data; and

implements a Fast Fourier Transform algorithm on the remaining coefficient data to transform the same data to coefficient data for convolution in the frequency domain, expanding the same on a memory.

13. The effect applying apparatus according to claim 12, wherein the setting unit

adds data indicating the decided block size to the coefficient data for convolution in the frequency domain and stores resultant data;

when the block size is decided again and only when the decided block size is different from the previously stored block size, implements the Fast Fourier Transform algorithm on the coefficient data for convolution in the frequency domain, thereby renewing the same coefficient data.

14. A method for implementing filter algorithm comprising the steps of:

reading coefficient data successively from a first memory which stores plural pieces of coefficient data to be used in the filter algorithm;

successively receiving plural pieces of input data to be subjected to the filter algorithm;

designating a filter order of the filter algorithm;

implementing the filter algorithm repeatedly on the coefficient data read successively from the coefficient storing unit and the successively received input data as many times as the number corresponding to the designated filter order, in which algorithm each piece of coefficient data and each piece of input data are multiplied together and resultant products are summed up, and

outputting a result of implementing the filter algorithm.

15. The method for implementing filter algorithm according to claim 14, wherein

the filter algorithm is a Finite Impulse Response (FIR) filter algorithm;

the first memory stores plural pieces of FIR coefficient data;

further comprising the steps of;

storing plural pieces of received input data in a second memory; and

implementing the FIR filter algorithm using the plural pieces of FIR coefficient data stored in the first memory and the plural pieces of received input data stored in the second memory as many times as the number corresponding to a designated filter order, in which filter algorithm each piece of FIR coefficient data and each piece of input data are multiplied together and resultant products are summed up.

16. The method for implementing filter algorithm according to claim 15, wherein

when an acoustic effect is applied to an original tone by convoluting the original tone with impulse response data of an acoustic effect tone, the FIR filter algorithm is implemented to convolute the original tone with first half data of the impulse response data in the time domain of unit of the sampling period;

and

a Fast Fourier Transform algorithm is implemented to convolute the original tone with second half data of the impulse response data in the frequency domain of unit of block.

17. The method for implementing filter algorithm according to claim 15, wherein

the first half data and the second half data of the impulse response data are set arbitrarily.