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• US 20180269111A1
• Filed: 05/17/2018
• Published: 09/20/2018
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHENG, Yu-Hung, TSAI, Ching-Wei, TU, Yeur-Luen, LIN, Tung-I, CHEN, Wei-Li
• Granted Patent: US 10,453,757 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

providing a first wafer comprising a substrate and a first semiconductor material layer;

bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer;

removing the sacrificial layer;

patterning the bonded first wafer and second wafer to create a first structure and a second structure;

removing the second semiconductor material layer from the first structure;

forming a first type of transistor in the first semiconductor material layer of the first structure; and

forming a second type of transistor in the second semiconductor material layer of the second structure.

2. The method of claim 1, further comprising forming a superlattice structure that alternates between two different semiconductor materials in a direction that is substantially perpendicular to the substrate, the two different semiconductor materials having a same type of dopant.

3. The method of claim 1, wherein forming the first type of transistor and the second type of transistor comprises epitaxially growing source/drain regions within the first semiconductor material layer and the second semiconductor material layer, the source/drain regions having vertexes pointed towards a region underneath a gate device.

4. The method of claim 1, wherein bonding the first wafer to the second wafer includes applying a bonding layer between the first semiconductor material layer and the second semiconductor material layer.

5. The method of claim 4, wherein the bonding layer is aluminum oxide (Al₂O₃).

6. The method of claim 1, wherein the forming the first type of transistor in the first semiconductor material layer includes removing a portion of the first semiconductor material layer and forming a source/drain material in a first region defined by the removed portion.

7. The method of claim 6, wherein the forming the second type of transistor in the second semiconductor material layer includes removing a second portion of the second semiconductor material layer and forming another source/drain material in a second region defined by the removed second portion.

8. The method of claim 6, wherein the first region has a shape with a tip extending toward a channel region under a gate structure of the first type of transistor.

9. The method of claim 8, further comprising:

forming a higher concentration of a dopant in the tip of the first region than a remaining portion of the first region.

10. A method for fabricating a semiconductor device, the method comprising:

providing a first substrate and a first semiconductor material layer;

providing a second substrate and a second semiconductor material layer, the second semiconductor material layer different in composition than the first semiconductor material layer;

bonding the first semiconductor material layer to the second semiconductor material layer by applying a bonding layer between the first and second semiconductor material layers;

patterning the bonded first semiconductor material layer and second semiconductor material layer to create a first structure having the first semiconductor material layer and a second structure having the first semiconductor material layer, the bonding layer, and the second semiconductor material layer;

forming a first type of transistor in the first semiconductor material layer of the first structure; and

forming a second type of transistor in the second semiconductor material layer of the second structure.

11. The method of claim 10, wherein the patterning the bonded first semiconductor material layer and second semiconductor material layer includes removing the second semiconductor material layer from a region including the first structure.

12. The method of claim 10, wherein the forming the first type of transistor includes etching a recess in the first semiconductor material layer, wherein the recess has a profile providing a tip facing a channel region under a gate of the first type of transistor.

13. The method of claim 12, further comprising:

filling the recess with source/drain material.

14. The method of claim 13, wherein the filling the recess includes providing a higher dopant concentration at the tip.

15. A method for fabricating a semiconductor device, the method comprising:

providing a first stack and a second stack over a substrate, each of the first stack and second stack including a first semiconductor material layer, a bonding layer, and a second semiconductor material layer, wherein the first stack is a spaced a distance from the second stack;

removing the second semiconductor material layer and the bonding layer from the first stack exposing the first semiconductor material layer;

forming a first gate structure on the first semiconductor material layer of the first stack and etching a first set of recesses in the first semiconductor material layer;

forming a second gate structure on the second semiconductor material layer of the second stack and etching a second set of recesses in the second semiconductor material layer; and

filling each of the first set of recesses and the second set of recesses with source/drain material.

16. The method of claim 15, wherein the filling each of the first set of recesses and the second set of recesses includes providing a first material in the first set of recesses and a second material, different than the first material in the second set of recesses.

17. The method of claim 15, wherein the etching the first set of recesses includes forming a recess having a vertex.

18. The method of claim 17, wherein the filling the first set of recesses includes forming a superlattice structure in each of the first set of recesses.

19. The method of claim 17, wherein the filling of the first set of recesses includes filling the recess having a higher dopant concentration toward the vertex.

20. The method of claim 15, wherein the filling each of the first set of recesses includes forming a superlattice structure in each of the first set of recesses.