SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• US 20180269153A1
• Filed: 05/17/2018
• Published: 09/20/2018
• Est. Priority Date: 10/24/2014
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Socionext Inc.
• Inventors: MATSUI, Tooru, YOSHIMURA, Masahiro
• Granted Patent: US 10,446,492 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.

Claims

1. A semiconductor integrated circuit device comprising:

at least two I/O cell rows each including a plurality of I/O cells arranged in a first direction;

a plurality of external connection pads; and

a common power supply interconnect that connects together a plurality of first I/O cells configured either as I/O cells for supplying a power supply potential or as I/O s for supplying a ground potential, the first I/O cells each included in a respective one of the at least two I/O cell rows, wherein

the first I/O cells connected together via the common power supply interconnect are arranged so as to overlap with each other in the first direction, and

the common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to a plurality of first pads which are included by the plurality of external connection pads and are located closest to the common power supply interconnect in the first direction among the plurality of external connection pads, and

the plurality of first pads are arranged at a same position in the first direction.

2. The semiconductor integrated circuit device of claim 1, wherein the first I/O cells have a same dimension and are arranged at a same position in the first direction.

3. The semiconductor integrated circuit device of claim 1, wherein at least one of the at least two I/O cell rows extends in a ring or frame shape entirely along a periphery of the semiconductor integrated circuit device.

4. The semiconductor integrated circuit device of claim 1, wherein the common power supply interconnect overlaps with at least one of the plurality of first pads in a plan view.

5. The semiconductor integrated circuit device of claim 1, wherein at least one of the plurality of first pads overlaps with at least one of the plurality of first I/O cells.

6. A semiconductor integrated circuit device comprising:

at least two I/O cell rows each including a plurality of I/O cells arranged in a first direction;

a plurality of external connection pads;

a first common power supply interconnect that connects together a plurality of first I/O cells configured either as I/O cells for supplying a power supply potential or as I/O cells for supplying a ground potential, the first I/O cells each included in a respective one of the at least two I/O cell rows; and

a second common power supply interconnect that connects together a plurality of second I/O cells configured either as I/O cells for supplying a power supply potential or as I/O cells for supplying a ground potential, the second I/O cells each included in a respective one of the at least two I/O cell rows, wherein

the first I/O cells connected together via the first common power supply interconnect are arranged so as to overlap with each other in the first direction,

the second I/O cells connected together via the second common power supply interconnect are arranged so as to overlap with each other in the first direction,

the first common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to a first pad which is included by the plurality of external connection pads and is located closest to the first common power supply interconnect in the first direction among the plurality of external connection pads,

the second common power supply interconnect extends in the second direction and is connected to a second pad which is included by the plurality of external connection pads, and

the first pad and the second pad are arranged at a same position in the first direction.

7. The semiconductor integrated circuit device of claim 6, wherein the first I/O cells have a same dimension and are arranged at a same position in the first direction.

8. The semiconductor integrated circuit device of claim 6, wherein at least one of the at least two I/O cell rows extends in a ring or frame shape entirely along a periphery of the semiconductor integrated circuit device.

9. The semiconductor integrated circuit device of claim 6, wherein the first common power supply interconnect is connected to at least two of the plurality of external connection pads, where the at least two of the plurality of external connection pads include the first pad.

10. The semiconductor integrated circuit device of claim 6, wherein the first common power supply interconnect overlaps with the first pad in a plan view.

11. The semiconductor integrated circuit device of claim 6, wherein the first pad overlaps with at least one of the plurality of first I/O cells.