SEMICONDUCTOR MEMORY

• US 20180269210A1
• Filed: 09/14/2017
• Published: 09/20/2018
• Est. Priority Date: 03/16/2017
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: TEZUKA, Tsutomu, Arai, Fumitaka, Ikeda, Keiji, Ueda, Tomomasa, Saito, Nobuyoshi, Tanaka, Chika, Miura, Kentaro
• Granted Patent: US 10,312,239 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/02 for one transistor one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

Claims

1. A semiconductor memory comprising:

a bit line;

a source line;

a pillar extending in a first direction from the bit line to the source line and including an oxide semiconductor layer;

first, second and third conductive layers disposed along the first direction and opposed to a side surface of the pillar;

a memory cell disposed at a first intersection between the first conductive layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer;

a first transistor disposed at a second intersection between the second conductive layer and the pillar; and

a second transistor disposed at a third intersection between the third conductive layer and the pillar,

wherein

a first end of the oxide semiconductor layer in the first direction is in contact with the source line, and

a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

2. The semiconductor memory according to claim 1, wherein

the oxide semiconductor layer extends from the first intersection to the source line by way of the second intersection and the third intersection,

the first transistor includes a first channel region in the oxide semiconductor layer, and

the second transistor includes a second channel region in the oxide semiconductor layer.

3. The semiconductor memory according to claim 1, wherein

the pillar includes a semiconductor layer extending in the first direction,

the memory cell includes a third channel region in the semiconductor layer,

a third end of the semiconductor layer in the first direction is in contact with the source line;

and

a fourth end of the semiconductor layer in the first direction is in contact with the bit line.

4. The semiconductor memory according to claim 1, wherein

the source line is provided on an insulating layer covering the first, second and third conductive layers, and

the oxide semiconductor layer is provided between a bottom portion of the source line and an upper portion of the insulating layer.

5. The semiconductor memory according to claim 1, further comprising:

a contact connected to the source line; and

a semiconductor layer provided in the pillar.

6. The semiconductor memory according to claim 5, wherein

the second conductive layer is located between the first conductive layer and the third conductive layer,

the contact is located inside the pillar and extends from the source line to a region between the first conductive layer and the second conductive layer by way of the second intersection and the third intersection, and

the semiconductor layer extends from the bit line to the contact by way of the first intersection.

7. The semiconductor memory according to claim 1, wherein

a threshold voltage of the memory cell varies in accordance with an amount of charges in the charge storage layer,

the memory cell retains first data where the threshold voltage of the memory cell is a first value, and

the memory cell retains second data different from the first data where the threshold voltage of the memory cell is a second value different from the first value.

8. The semiconductor memory device according to claim 7, wherein

the charges are supplied from the source line to the oxide semiconductor layer.

9. A semiconductor memory comprising:

a semiconductor layer disposed on a substrate and extending in a first direction;

an oxide semiconductor layer disposed above the semiconductor layer, with a first insulating layer interposed;

a first gate electrode disposed above the oxide semiconductor layer, with a second insulating layer interposed;

a second gate electrode disposed above the oxide semiconductor layer and adjacent to the first gate electrode in the first direction;

a charge storage layer disposed in the oxide semiconductor layer below the first gate electrode;

a bit line connected to one end of the semiconductor layer in the first direction, and to one end of the oxide semiconductor layer in the first direction; and

a source line connected to other end of the semiconductor layer in the first direction.

10. The semiconductor memory according to claim 9, further comprising:

a memory cell including the first gate electrode and the charge storage layer; and

a transistor including the second gate electrode and a channel region of the oxide semiconductor layer.

11. The semiconductor memory according to claim 10, wherein

a threshold voltage of the memory cell varies in accordance with an amount of charges in the charge storage layer,

the memory cell retains first data where the threshold voltage of the memory cell is a first value, and

the memory cell retains second data different from the first data where the threshold voltage of the memory cell is a second value different from the first value.

12. The semiconductor memory according to claim 9, further comprising:

a back gate electrode disposed below the semiconductor layer.

13. The semiconductor memory according to claim 9, wherein

the bit line extends in the first direction, and the source line extends in a second direction intersecting with the first direction.

14. The semiconductor memory according to claim 9, wherein

the bit line and the source line extend in the first direction.

15. A semiconductor memory comprising:

a semiconductor layer disposed on a substrate and extending in a first direction;

an oxide semiconductor layer disposed above the semiconductor layer, with a first insulating layer interposed;

a first gate electrode disposed above the oxide semiconductor layer, with a second insulating layer interposed;

a second gate electrode disposed above the oxide semiconductor layer and adjacent to the first gate electrode in the first direction;

a charge storage layer disposed in the oxide semiconductor layer below the first gate electrode;

a bit line connected to a first end of the semiconductor layer in the first direction;

a source line connected to a second end of the semiconductor layer in the first direction; and

an injection line connected to a third end which is in the oxide semiconductor layer and located close to the second gate electrode.

16. The semiconductor memory according to claim 15, further comprising:

a memory cell including the first gate electrode and the charge storage layer; and

a transistor including the second gate electrode and a channel region in the oxide semiconductor layer.

17. The semiconductor memory according to claim 16, wherein

a threshold voltage of the memory cell varies in accordance with an amount of charges in the charge storage layer,

the memory cell retains first data where the threshold voltage of the memory cell is a first value, and

the memory cell retains second data different from the first data where the threshold voltage of the memory cell is a second value different from the first value.

18. The semiconductor memory according to claim 15, further comprising:

a back gate electrode disposed below the semiconductor layer.

19. The semiconductor memory according to claim 15, wherein

the bit line extends in the first direction, and

the source line extends in a second direction intersecting with the first direction.

20. The semiconductor memory according to claim 15, wherein

the bit line and the source line extend in the first direction.