3D Semiconductor Device and Structure

• US 20180269229A1
• Filed: 09/21/2016
• Published: 09/20/2018
• Est. Priority Date: 09/21/2015
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Han, Jin-Woo
• Granted Patent: US 10,515,981 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 2027/11838 Implementation of memory functions
• CPC Class Codes: H01L 2027/11888 More than 3 levels of metal
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor

Abstract

A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.

Claims

1-30. -30. (canceled)

31. A multilevel semiconductor device, the device comprising:

a first level comprising a first array of first memory cells and a first control line;

a second level comprising a second array of second memory cells and a second control line;

a third level comprising a third array of third memory cells and a third control line,

wherein said second level overlays said first level, and

wherein said third level overlays said second level;

a first access pillar;

a second access pillar; and

a third access pillar,

wherein said first memory cells are self-aligned to said second memory cells,

wherein said first access pillar has a first electrically programmable connection to said first control line,

wherein said second access pillar has a second electrically programmable connection to said second control line, and

wherein said third access pillar has a third electrically programmable connection to said third control line.

32. The device according to claim 31,

wherein said electrically programmable comprises a One Time Programmable (“

OTP”

) structure.

33. The device according to claim 31,

wherein said electrically programmable comprises a Resistive Programmable structure.

34. The device according to claim 31,

wherein said second control line comprises a horizontal transistor designed to be used for said electrically programmable connection.

35. The device according to claim 31, further comprising:

a control circuit designed to be used for said electrically programmable connection.

36. The device according to claim 31,

wherein said device is designed to use said third electrically programmable connection of said third access pillar for the programming of said second electrically programmable connection of said second access pillar.

37. The device according to claim 31,

wherein said first access pillar has un-activated electrically programmable connections to said second control line and to said third control lines.

38. A multilevel semiconductor device, the device comprising:

a first level comprising a first array of first programmable cells and a first control line;

a second level comprising a second array of second programmable cells and a second control line; and

a third level comprising a third array of third programmable cells and a third control line,

wherein said second level overlays said first level,

wherein said third level overlays said second level,

wherein said first programmable cells are self-aligned to said second programmable cells, and

wherein a programmable logic cell comprises a plurality of said first programmable cells and a plurality of said second programmable cells.

39. The device according to claim 38,

wherein said programmable logic cell is a programmable Look-Up-Table (“

LUT”

) cell.

40. The device according to claim 38,

wherein said programmable cells comprises a charge trap structure or a floating gate structure.

41. The device according to claim 38, further comprising:

a plurality of conductive pillars,

wherein a plurality of said conductive pillars and said control lines are connected by electrically programmable connections.

42. The device according to claim 38,

wherein said second control line comprises a plurality of horizontal transistors.

43. The device according to claim 38,

wherein said first control line is designed for at least a first function and a second function,

wherein said first function is to provide access for programming said first programmable cells, and

wherein said second function is providing connectivity for said programmable logic cell.

44. The device according to claim 38, further comprising:

a fourth level comprising a fourth array of non-programmable cells supporting the functionality of said programmable logic cells,

wherein said fourth level overlays said third level.

45. A multilevel semiconductor device, the device comprising:

a first level comprising a first array of first memory cells and a first control line;

a second level comprising a second array of second memory cells and a second control line;

a third level comprising a third array of third memory cells and a third control line,

wherein said second level overlays said first level, and

wherein said third level overlays said second level;

a first access pillar;

a second access pillar;

a third access pillar; and

a memory control level comprising memory control circuits designed to individually control every cell of said first memory cells, second memory cells and third memory cells,

wherein said memory control level overlays said third level or underlays said first level,

wherein said device comprises an array of units,

wherein each of said units comprises a plurality of said first memory cells, said second memory cells, said third memory cells, and a portion of said memory control circuits,

wherein said array of units comprise at least four rows and four columns of units, and

wherein said memory control circuits are designed to control independently each of said units.

The device according to claim 45, wherein said first access pillar has a first electrically programmable connection to said first control line.

47. The device according to claim 45,

wherein at least one of said first memory cells is self-aligned to at least one of said third memory cells.

48. The device according to claim 45,

wherein said memory cells comprise a charge trap structure or a floating gate structure.

49. The device according to claim 45,

wherein said control comprises that a memory cell of one unit could be read while another memory cell is being read from another memory unit.

50. The device according to claim 45, further comprising:

a feed-through conductive path through said first level, said second level and said third level.