Shift Register Unit and Driving Method Thereof, Shift Register and Display Device

• US 20180277043A1
• Filed: 10/18/2016
• Published: 09/27/2018
• Est. Priority Date: 10/23/2015
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Li, Quanhu, Li, Yongqian, Meng, Song
• Granted Patent: US 10,573,245 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register unit and a driving method thereof, shift register and display device. The shift register unit including an input circuit (P1), a pull-down control circuit (P2), a pull-up control circuit (P3), a pull-up circuit (P4) and a pull-down circuit (P5); wherein the input circuit (P1) is connected to a first trigger signal end (STU), a first clock signal end (CLK1), a power level end (VGL) and a pull-up control node (Q), and is for utilizing a bootstrap effect to transfer a signal of the first trigger signal end (STU) to the pull-up control node (Q) without a threshold voltage loss. The shift register unit is for use in a display device, and resolves the problem of a display device having a non-uniform display, resulting in a poor displaying effect of a display device.

Claims

1. A shift register unit, comprising:

an input circuit, connected to a first trigger signal end, a first clock signal end, a low level end and a pull-up control node, and configured to transmit a signal of the first trigger signal end to the pull-up control node by a bootstrap effect without a threshold voltage loss;

a pull-down control circuit, connected to the first clock signal end, the pull-up control node, a pull-down control node and the low level end and configured to control a signal of the pull-down control node to be a high level signal or a low level signal according to a signal of the first clock signal end and a signal of the pull-up control node;

a pull-up control circuit, connected to a second trigger signal end, the low level end, the pull-up control node, the pull-down control node, and an output terminal of the shift register unit, and configured to control the signal of the pull-up control node to be the high level signal or the low level signal according to a signal of the second trigger end and the bootstrap effect;

a pull-up circuit, connected to the first clock signal end, the pull-up control node and the output terminal of the shift register unit, and configured to pull up a signal of the output terminal of the shift register unit as the high level signal under the control of the signal of the pull-up control node and the signal of the first clock signal end; and

a pull-down circuit, connected to the second trigger signal end, the low level end, a second clock signal end, the pull-down control node, the pull-up control node and the output terminal of the shift register unit, and configured to pull down the signal of the output terminal of the shift register unit as the low level signal according to the signal of the pull-down control node, the signal of the second trigger signal end and a signal of the second clock signal end,

wherein the pull-up control node is a connection point of the input circuit, the pull-up control circuit, the pull-down control circuit and the pull-up circuit, and the pull-down control node is a connection point of the pull-down control circuit, the pull-up control circuit and the pull-down circuit.

2. The shift register unit according to claim 1, wherein the input circuit comprises a first transistor, a second transistor, a third transistor and a first capacitor;

a gate of the first transistor is connected to the first trigger signal end, a first electrode thereof is connected to a second electrode of the second transistor and a first electrode of the first capacitor, and a second electrode thereof is connected to the first trigger signal end;

a gate of the second transistor is connected to the first clock signal end, a first electrode thereof is connected to the low level end, and the electrode thereof is connected to the first electrode of the first capacitor;

a gate of the third transistor is connected to the first electrode of the first capacitor, a first electrode thereof is connected to the pull-up control node and a second electrode of the first capacitor, and a second electrode thereof is connected to the first trigger signal end; and

the second electrode of the first capacitor is connected to the pull-up control node.

3. The shift register unit according to claim 1, wherein the pull-down control circuit comprises a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

a gate of the fourth transistor is connected to the first clock signal end, a first electrode thereof is connected to a gate of the fifth transistor and a second electrode of the sixth transistor, and a second electrode thereof is connected to the first clock signal end;

the gate of the fifth transistor is connected to the second electrode of the sixth transistor, a first electrode thereof is connected to a second electrode of the seventh transistor and the pull-down control node, and a second electrode thereof is connected to the first clock signal end;

a gate of the sixth transistor is connected to the pull-up control node, and a first electrode thereof is connected to the low level end; and

a gate of the seventh transistor is connected to the pull-up control node, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to the pull-down control node.

4. The shift register unit according to claim 1, wherein the pull-up control circuit comprises an eighth transistor, a ninth transistor and a second capacitor;

a gate of the eighth transistor is connected to the second trigger signal end, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to the pull-up control node;

a gate of the ninth transistor is connected to the pull-down control node, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to a first electrode of the second capacitor and the pull-up control node; and

the first electrode of the second capacitor is connected to the pull-up control node, and a second electrode thereof is connected to the pull-down circuit and the output terminal of the shift register unit.

5. The shift register unit according to claim 1, wherein the pull-up circuit comprises a tenth transistor;

a gate of the tenth transistor is connected to the pull-up control node, a first electrode thereof is connected to the output terminal of the shift register unit, and a second electrode thereof is connected to the first clock signal end.

6. The shift register unit according to claim 1, wherein the pull-down circuit comprises a eleventh transistor, a twelfth transistor and a thirteenth transistor;

a gate of the eleventh transistor is connected to the pull-down control node, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to the output terminal of the shift register unit;

a gate of the twelfth transistor is connected to the second trigger signal end, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to a first electrode of the thirteen transistor and the output terminal of the shift register; and

a gate of the thirteenth transistor is connected to the second clock signal end, the first electrode thereof is connected to the output terminal of the shift register, and a second electrode thereof is connected to the low level end.

7. A driving method of a shift register unit for driving the shift register unit according to claim 1, the driving method comprises:

in a first phase, making both a signal of a first trigger signal end and a signal of a second clock signal end into a high level signal, and making both a signal of a second trigger signal end and a signal of a first clock signal end into a low level signal;

transmitting, by an input circuit, the high level signal of the first trigger signal end to the pull-up control node by using a bootstrap effect without a threshold voltage loss;

transmitting, by a pull-up circuit, a low level signal of the first clock signal end to an output terminal of the shift register unit under the control of a high level signal of the pull-up control node and the low level signal of the first clock signal end; and

outputting the low level signal at the output terminal of the shift register unit;

in a second phase, making both the signal of the first trigger signal end, the signal of the second clock signal end and the signal of the second trigger signal end into the low level signal, and making the signal of the first clock signal end into the high level signal;

controlling, by a pull-up control circuit, the signal of the pull-up control node into the high level signal by using the bootstrap effect;

pulling up, by the pull-up circuit, the signal of the output terminal of the shift register unit into the high level signal under the control of the high level signal of the pull-up control node and the high level signal of the first clock signal end;

in a third phase, making both the signal of the first trigger signal end and the signal of the first clock signal end into the low level signal, and making the signal of the second trigger signal end and the signal of the second clock signal end into the high level signal;

controlling, by the pull-up control circuit, the signal of the pull-up control node to be the low level signal according to the high level signal of the second trigger signal end; and

pulling down, by a pull-down circuit, the signal of the output terminal of the shift register unit into the low level signal under the control of the high level signal of the second trigger signal end and the high level signal of the second clock signal end;

in a fourth phase, making the signal of the first trigger signal end, the signal of the second clock signal end and the signal of the second trigger signal end into the low level signal, and making the signal of the first clock signal end into the high level signal;

controlling, by a pull-down control circuit, a signal of a pull-down control node to be the high level signal under the control of the high level signal of the first clock signal end and the low level signal of the pull-up control node; and

pulling down, by the pull-down circuit, the signal of the output terminal of the shift register unit into the low level signal under the control of the high level signal of the pull-down control node;

in a fifth phase, making the signal of the first trigger signal end, the signal of the first clock signal end and the signal of the second trigger signal end into the low level signal, and the signal of the second clock signal end into the high level signal; and

pulling down, by the pull-down circuit, the signal of the output terminal of the shift register unit into the low level signal under the control of the high level signal of the second clock signal end.

8. The driving method of the shift register unit according to claim 7, further comprising:

in the first phase;

making the first transistor turned on by receiving the high level signal of the first trigger signal end;

raising a gate voltage of the third transistor through the first capacitor by using its own bootstrap effect, so that the third transistor is fully turned on; and

transmitting the high level signal of the first trigger signal end to the pull-up control node without a threshold voltage loss through the third transistor;

making the tenth transistor turned on by receiving the high level signal of the pull-up control node; and

transmitting the low level signal of the first clock signal to the output terminal of the shift register unit through the tenth transistor; and

outputting the low level signal at the output terminal of the shift register nit.

9. The driving method of the shift register unit according to claim 7, further comprising:

in the second phase;

raising the signal of the pull-up control node to the high level signal through the second capacitor by using its own bootstrap effect;

making the tenth transistor turned on by receiving the high level signal of the pull-up control node; and

transmitting the high level signal of the first clock signal end to the output terminal of the shift register unit through the tenth transistor; and

pulling up the signal of the output terminal of the shift register to the high level signal.

10. The driving method of the shift register unit according to claim 7, further comprising:

in the third phase;

making both the eighth transistor and the twelfth transistor turned on by receiving the high level signal of the second trigger signal end;

transmitting the low level signal of the low level end to the pull-up control node through the eighth transistor, and making the tenth transistor turned off by receiving the low level signal of the pull-up control node;

transmitting the low level signal of the low level end to the output terminal of the shift register unit through the twelfth transistor; and

pulling down the signal of the output terminal of the shift register unit to the low level signal.

11. The driving method of the shift register unit according to claim 7, further comprising:

in the fourth phase;

making the fourth transistor turned on by receiving the high level signal of the first clock signal end;

transmitting the high level signal of the first clock signal end to the gate of the fifth transistor through the fourth transistor, so that the fifth transistor is turned on;

transmitting the high level signal of the first clock signal end to the pull-down control node through the fifth transistor;

making both the ninth transistor and the eleventh transistor turned on by receiving the high level signal of the pull-down control node;

transmitting the low level signal of the low level end to the pull-up control node through the ninth transistor, and making the tenth transistor turned off by receiving the low level signal of the pull-up control node;

transmitting the low level signal of the low level end to the output terminal of the shift register unit through the eleventh transistor; and

pulling down the signal of the output terminal of the shift register unit as the low level signal.

12. The driving method of the shift register unit according to claim 7, further comprising:

in the fifth phase;

making the thirteenth transistor turned on by receiving the high level signal of the second clock signal end;

transmitting the low level signal of the low level end to the output terminal of the shift register unit through the thirteen transistor; and

pulling down the output terminal of the shift register unit as the low level signal.

13. A shift register, comprising the shift register unit according to claim 1.

14. A display device, comprising the shift register according to claim 13.

15. The shift register according to claim 13, wherein the input circuit comprises a first transistor, a second transistor, a third transistor and a first capacitor;

a gate of the first transistor is connected to the first trigger signal end, a first electrode thereof is connected to a second electrode of the second transistor and a first electrode of the first capacitor, and a second electrode thereof is connected to the first trigger signal end;

a gate of the second transistor is connected to the first clock signal end, a first electrode thereof is connected to the low level end, and the electrode thereof is connected to the first electrode of the first capacitor;

a gate of the third transistor is connected to the first electrode of the first capacitor, a first electrode thereof is connected to the pull-up control node and a second electrode of the first capacitor, and a second electrode thereof is connected to the first trigger signal end; and

the second electrode of the first capacitor is connected to the pull-up control node.

16. The shift register according to claim 13, wherein the pull-down control circuit comprises a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

a gate of the fourth transistor is connected to the first clock signal end, a first electrode thereof is connected to a gate of the fifth transistor and a second electrode of the sixth transistor, and a second electrode thereof is connected to the first clock signal end;

the gate of the fifth transistor is connected to the second electrode of the sixth transistor, a first electrode thereof is connected to a second electrode of the seventh transistor and the pull-down control node, and a second electrode thereof is connected to the first clock signal end;

a gate of the sixth transistor is connected to the pull-up control node, and a first electrode thereof is connected to the low level end; and

a gate of the seventh transistor is connected to the pull-up control node, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to the pull-down control node.

17. The shift register according to claim 13, wherein the pull-up control circuit comprises an eighth transistor, a ninth transistor and a second capacitor;

a gate of the eighth transistor is connected to the second trigger signal end, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to the pull-up control node;

a gate of the ninth transistor is connected to the pull-down control node, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to a first electrode of the second capacitor and the pull-up control node; and

the first electrode of the second capacitor is connected to the pull-up control node, and a second electrode thereof is connected to the pull-down circuit and the output terminal of the shift register unit.

18. The shift register according to claim 13, wherein the pull-up circuit comprises a tenth transistor;

a gate of the tenth transistor is connected to the pull-up control node, a first electrode thereof is connected to the output terminal of the shift register unit, and a second electrode thereof is connected to the first clock signal end.

19. The shift register according to claim 13, wherein the pull-down circuit comprises a eleventh transistor, a twelfth transistor and a thirteenth transistor;

a gate of the eleventh transistor is connected to the pull-down control node, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to the output terminal of the shift register unit;

a gate of the twelfth transistor is connected to the second trigger signal end, a first electrode thereof is connected to the low level end, and a second electrode thereof is connected to a first electrode of the thirteen transistor and the output terminal of the shift register; and

a gate of the thirteenth transistor is connected to the second clock signal end, the first electrode thereof is connected to the output terminal of the shift register, and a second electrode thereof is connected to the low level end.

20. The display device according to claim 14, wherein the input circuit comprises a first transistor, a second transistor, a third transistor and a first capacitor;

a gate of the first transistor is connected to the first trigger signal end, a first electrode thereof is connected to a second electrode of the second transistor and a first electrode of the first capacitor, and a second electrode thereof is connected to the first trigger signal end;

a gate of the second transistor is connected to the first clock signal end, a first electrode thereof is connected to the low level end, and the electrode thereof is connected to the first electrode of the first capacitor;

a gate of the third transistor is connected to the first electrode of the first capacitor, a first electrode thereof is connected to the pull-up control node and a second electrode of the first capacitor, and a second electrode thereof is connected to the first trigger signal end; and

the second electrode of the first capacitor is connected to the pull-up control node.