NONVOLATILE MEMORY DEVICES PROVIDING REDUCED DATA LINE LOAD

• US 20180277225A1
• Filed: 02/20/2018
• Published: 09/27/2018
• Est. Priority Date: 03/22/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jeung-hwan
• Granted Patent: US 10,460,813 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A nonvolatile memory device according to sore embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.

Claims

1. A nonvolatile memory device comprising:

a memory cell array;

a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising a first bit line selection circuit connected to the first plurality of bit lines, a first bit line shut-off circuit connected to the first plurality of bit lines via the first bit line selection circuit, and a first latch circuit configured to input and output data via a first data line; and

a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising a second bit line selection circuit connected to the second plurality of bit lines, a second bit line shut-off circuit connected to the second plurality of bit lines via the second bit line selection circuit, and a second latch circuit configured to input and output data via a second data line,

wherein the first bit line selection circuit and the second bit line selection circuit are on a first region of a main surface of a substrate, the first bit line shut-off circuit and the second bit line shut-off circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on -a third region of the main surface of the substrate,

wherein the first region, the second region, and the third region arc sequentially arranged on the main surface of the substrate in a direction away from the memory cell array, and

wherein a width of the first, data line and a width of the second data line are each greater than a width of each of the first plurality of bit lines and a width of each of the second plurality of bit lines.

2. The nonvolatile memory device of claim 1, further comprising:

a plurality of layers on the substrate,

wherein the first data line and the second data line are connected to the first latch circuit and the second latch circuit, respectively, on a first layer of the plurality of layers.

3. The nonvolatile memory device of claim 2, wherein the first plurality of bit lines and the second plurality of bit lines are on the first layer.

4. The nonvolatile memory device of claim 1,

wherein the first page buffer further comprises a first discharge circuit that is configured to discharge the first plurality of bit lines, the first discharge circuit being between the first but line selection circuit and the first latch circuit, and

wherein the second page buffer further comprises a second discharge circuit that is configured to discharge the second plurality of bit lines, the second discharge circuit being between the second bit line selection circuit and the second latch circuit in the direction away from the memory cell array.

5. The nonvolatile memory device of claim 4,

wherein the first discharge circuit comprises a first discharge transistor comprising a first discharge transistor gate line,

wherein the second discharge circuit comprises a second discharge transistor comprising a second discharge transistor gate line,

wherein the first bit line selection circuit comprises a first selection transistor comprising a first selection transistor gate line,

wherein the second bit line selection circuit comprises a second selection transistor comprising a second selection transistor gate line, and

wherein a thickness of the first discharge transistor gate line and a thickness of the second discharge transistor gate line are each less than a thickness of the first selection transistor gate line and a thickness of the second selection transistor gate line.

6. The nonvolatile memory device of claim 1,

wherein the first latch circuit comprises a first main latch and a first cache latch,

wherein the second latch circuit comprises a second main latch and a second cache latch, and

wherein the first main latch, the first cache latch, the second main latch, and the second cache latch are sequentially arranged on the main surface of the substrate in the direction away from the memory cell array.

7. The nonvolatile memory device of claim 1,

wherein the first latch circuit comprises a first data latch and a first cache latch,

wherein the second latch circuit comprises a second data latch and a second cache latch, and

wherein the first data, latch, the second data latch, the first cache latch, and the second cache latch are sequentially arranged on the main surface of the substrate in the direction away from the memory cell array.

8. A nonvolatile memory device comprising:

a memory cell array;

a first page buffer connected to the memory cell array via a first plurality of bit lines, the first page buffer comprising a first high-voltage circuit connected to the first plurality of bit lines, a first low-voltage circuit connected to the first plurality of bit lines via the first high-voltage circuit, and a first latch circuit configured to input and output data via a first data line; and

a second page buffer connected to the memory cell array via a second plurality of bit lines, the second page buffer comprising ,a second high-voltage circuit connected to the second plurality of bit lines, a second low-voltage circuit connected to the second plurality of bit lines via the second high-voltage circuit, and a second latch circuit configured to input and output data via a second data line,

wherein the first high-voltage circuit and the second high-voltage circuit are on a first region of a main surface of a substrate, the first low-voltage circuit and the second low-voltage circuit are on a second region of the main surface of the substrate, and the first latch circuit and the second latch circuit are on a third region of the main surface of the substrate,

wherein the first region, the second region, and the third region are sequentially arranged on, the main surface of the substrate in a direction away from the memory cell array, and

wherein the first high-voltage circuit and the second high-voltage circuit are configured to receive respective voltages comprising higher ranges than voltages that the first low-voltage circuit and the second low-voltage circuit are configured to receive.

9. The nonvolatile memory device of claim 8,

wherein a width of the first data line and a width of the second data line are each greater than a width of each of the first plurality of bit lines and a width of each of the second plurality of bit lines.

10. The nonvolatile memory device of claim 8,

wherein the first plurality of bit lines comprise a first bit line of a first bit line group and a second bit line of a second bit line group,

wherein the second plurality of bit lines comprise a third bit line of the first bit line group and a fourth bit line of the second bit line group,

wherein the first page buffer is connected to the first bit line of the first bit line group and the second bit line of the second bit line group, and

wherein the second page buffer is connected to the third bit line of the first bit line group and the fourth bit line of the second bit line group.

11. The nonvolatile memory device of claim 8,

wherein the first high-voltage circuit comprises a plurality of selection transistors connected to respective ones of the first plurality of bit lines, and

wherein the first low-voltage circuit comprises a shut-off transistor configured to perfoim a shut-off operation of at least one of the first plurality of bit lines.

12. The nonvolatile memory device of claim 8, wherein the first low-voltage circuit comprises a plurality of discharge transistors that are configured to discharge respective ones of the first plurality of bit lines.

13. The nonvolatile memory device of claim 8, wherein the first high-voltage circuit comprises a plurality of discharge transistors that are configured to discharge respective ones of the first plurality of bit lines.

14. The nonvolatile memory device of claim 8, wherein the first low-voltage circuit is configured to transmit an output signal to the first latch circuit via a sensing node.

15. A nonvolatile memory device comprising:

a memory cell array; and

a page buffer circuit including a plurality of high-voltage circuits, a plurality of low-voltage circuits, and a plurality of latch circuits on a substrate,

wherein, the substrate includes a high-voltage region in which the high-voltage circuits are arranged, a low-voltage region in which the low-voltage circuits are arranged, and latch region in which the latch circuits are arranged,

wherein the high-voltage region, the low-voltage region, and the latch region are sequentially arranged on a main surface of the substrate in a direction away from the memory cell array,

wherein a plurality of bit line patterns are formed on the high-voltage region and the low-voltage region,

wherein a plurality of data line patterns are formed on the high-voltage region and the latch region, and

wherein widths of the plurality of data line patterns are greater than widths of the bit line patterns.

16. The nonvolatile memory device of claim 15, wherein the plurality of bit line patterns and the plurality of data line patterns are formed in a single layer of the substrate.

17. The nonvolatile memory device of claim 15,

wherein a plurality of gate patterns are formed on the high-voltage region, a plurality of gate patterns are formed on the low-voltage region, and widths of the gate patterns in the high-voltage region are greater than widths of the gate patterns in the low-voltage region, respectively.

18. The nonvolatile memory device of claim 15,

wherein each of the plurality of high-voltage circuits comprises a first bit line selection transistor and a second bit line selection transistor, the first bit line selection transistor being electrically connected to the memory cell array via a first bit line pattern of the plurality of bit line patterns and the second bit line selection transistor being electrically connected to the memory cell array via a second bit line pattern of the plurality of bit line patterns,

wherein each of the plurality of low-voltage circuits comprises a first shut-off transistor and a second shut-off transistor, the first shut-off transistor electrically connecting the first bit line selection transistor and a sensing nod, and the second shut-off transistor electrically connecting the second bit line selection transistor and a sensing node.

19. The nonvolatile memory device of claim 18,

wherein a first width of a first active pattern of the first bit line selection transistor is greater than a second width of a second active pattern of the first shut-off transistor,

wherein a first thickness of a first gate line pattern of the first bit line selection transistor is greater than a second thickness of a second gate line pattern of the first shut-off transistor, and

wherein a third thickness of a first insulating layer between the first gate line pattern arid the first active pattern is greater than a fourth thickness of a second insulating layer between the second gate line pattern and the second active pattern.

20. The nonvolatile memory device of claim 15,

wherein each of the plurality of high-voltage circuits comprises a first bit line selection transistor and a second bit line selection transistor, the first bit line selection transistor being electrically connected to the memory cell array via a first bit line pattern of the plurality of bit line patterns and the second bit line selection transistor being electrically connected to the memory cell array via a second bit line pattern of the plurality of bit line patterns,

wherein each of the plurality of low-voltage circuits comprises a shut-off transistor, the shut-off transistor electrically connecting the first bit line selection transistor and a sensing nod, and the second, bit line selection transistor and a sensing node.