SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20180277438A1
• Filed: 03/14/2018
• Published: 09/27/2018
• Est. Priority Date: 03/24/2017
• Status: Active Grant

• Current Assignee: Asahi Kasei Microdevices Corporation (Asahi Kasei Corporation)
• Original Assignee: Asahi Kasei Microdevices Corporation (Asahi Kasei Corporation)
• Inventors: FUJII, Shuntaro, YAGI, Tatsushi, HAMADA, Shohei
• Granted Patent: US 10,438,951 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.

Claims

1. A manufacturing method of a semiconductor device, comprising:

forming an element separation layer on a semiconductor substrate;

forming a first well layer by implanting impurities of a first conductivity type into a digital circuit forming area of the semiconductor substrate;

forming a second well layer by implanting impurities of the first conductivity type into an analog circuit forming area of the semiconductor substrate, which is separated from the digital circuit forming area by the element separation layer;

forming a gate insulating film on a surface of the semiconductor substrate;

forming a first gate electrode on a surface of the gate insulating film in the digital circuit forming area and forming a second gate electrode on the surface of the gate insulating film in the analog circuit forming area;

forming a digital side second conductivity type impurity layer by implanting impurities of a second conductivity type into the first well layer using the first gate electrode as a mask;

forming an analog side second conductivity type impurity layer by implanting impurities of the second conductivity type into the second well layer using the second gate electrode as a mask;

forming sidewalls made of insulating films on side surfaces of respective ones of the first gate electrode and the second gate electrode;

forming a first source region and a first drain region by implanting impurities of the second conductivity type into the digital side second conductivity type impurity layer using the first gate electrode and the sidewall as a mask;

forming a second source region and a second drain region by implanting impurities of the second conductivity type into the analog side second conductivity type impurity layer using the second gate electrode and the sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the forming the first source region and the first drain region; and

forming silicide films on surfaces of the first source region, the first drain region, and the first gate electrode and the second source region, the second drain region, and the second gate electrode.

2. The manufacturing method of the semiconductor device according to claim 1, wherein

in the forming the analog side second conductivity type impurity layer, the implantation amount of the impurities of the second conductivity type is set smaller than that in the forming the digital side second conductivity type impurity layer.

3. The manufacturing method of the semiconductor device according to claim 1, wherein

in the forming the digital side second conductivity type impurity layer, arsenic is used as the impurities of the second conductivity type, and

in the forming the analog side second conductivity type impurity layer, phosphorus is used as the impurities of the second conductivity type.

4. The manufacturing method of the semiconductor device according to claim 1, wherein

in the forming the second source region and the second drain region, the implantation amount of the impurities of the second conductivity type is set smaller than that in the forming the first source region and the first drain region.

5. The manufacturing method of the semiconductor device according to claim 1, wherein

in the forming the second well layer, fluorine or carbon is co-implanted in conjunction with the impurities of the first conductivity type.

6. The manufacturing method of the semiconductor device according to claim 1, wherein

in at least one of the forming the analog side second conductivity type impurity layer and the forming the second source region and the second drain region, fluorine or carbon is co-implanted in conjunction with the impurities of the second conductivity type.

7. The manufacturing method of the semiconductor device according to claim 1, wherein

in the forming the second well layer, the impurities of the first conductivity type are implanted so that concentration of the impurities of the first conductivity type increases in a depth direction of the semiconductor substrate.

8. A manufacturing method of a semiconductor device, comprising:

forming an element separation layer on a semiconductor substrate;

forming a first well layer by implanting impurities of a first conductivity type into a digital circuit forming area of the semiconductor substrate;

forming a second well layer by implanting impurities of the first conductivity type into an analog circuit forming area of the semiconductor substrate, which is separated from the digital circuit forming area by the element separation layer;

forming a non-doped film by selectively growing the non-doped film on a surface of the semiconductor substrate in the analog circuit forming area;

forming gate insulating films on a surface of the semiconductor substrate in the digital circuit forming area and a surface of the non-doped film in the analog circuit forming area;

forming a first gate electrode on a surface of the gate insulating film in the digital circuit forming area and forming a second gate electrode on a surface of the gate insulating film in the analog circuit forming area;

forming a digital side second conductivity type impurity layer and an analog side second conductivity type impurity layer by implanting impurities of a second conductivity type into the first well layer and the non-doped film with a mean range shallower than or equal to thickness of the non-doped film;

forming sidewalls made of insulating films on side surfaces of respective ones of the first gate electrode and the second gate electrode;

forming a first source region and a first drain region in the digital side second conductivity type impurity layer and forming a second source region and a second drain region in the analog side second conductivity type impurity layer by implanting impurities of the second conductivity type into the digital side second conductivity type impurity layer and the analog side second conductivity type impurity layer using the first gate electrode, the second gate electrode, and the sidewalls as masks; and

forming silicide films on surfaces of the first source region, the first drain region, and the first gate electrode and the second source region, the second drain region, and the second gate electrode.

9. The manufacturing method of the semiconductor device according to claim 8, wherein

the forming the digital side second conductivity type impurity layer and the analog side second conductivity type impurity layer includes:

forming the digital side second conductivity type impurity layer by implanting impurities of the second conductivity type into the first well layer using the first gate electrode as a mask; and

forming the analog side second conductivity type impurity layer by implanting impurities of the second conductivity type into the second well layer using the second gate electrode as a mask.

10. The manufacturing method of the semiconductor device according to claim 8, wherein

the forming the first source region, the first drain region, the second source region, and a second drain region includes:

forming the first source region and the first drain region by implanting the impurities of the second conductivity type into the digital side second conductivity type impurity layer using the first gate electrode and the sidewall as a mask; and

forming the second source region and the second drain region by implanting impurities of the second conductivity type into the analog side second conductivity type impurity layer using the second gate electrode and the sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the forming the first source region and the first drain region.

11. A semiconductor device, comprising:

an element separation layer formed on a semiconductor substrate to separate the semiconductor substrate into a digital circuit forming area and an analog circuit forming area;

a first well layer of a first conductivity type formed in the digital circuit forming area;

a second well layer of the first conductivity type formed in the analog circuit forming area;

a first gate insulating film formed on a surface of the first well layer;

a second gate insulating film formed on a surface of the second well layer;

a first gate electrode formed on a surface of the first gate insulating film;

a second gate electrode formed on a surface of the second gate insulating film;

sidewalls formed of insulating films on side surfaces of respective ones of the first gate electrode and the second gate electrode;

a first source region and a first drain region of a second conductivity type formed in the first well layer with the first gate electrode interposed therebetween;

a second source region and a second drain region of the second conductivity type formed in the second well layer with the second gate electrode interposed therebetween and have a shallower depth from a surface of the semiconductor substrate than the first source region and the first drain region; and

silicide films formed on surfaces of the first source region, the first drain region, and the first gate electrode and the second source region, the second drain region, and the second gate electrode.

12. A semiconductor device, comprising:

an element separation layer formed on a semiconductor substrate to separate the semiconductor substrate into a digital circuit forming area and an analog circuit forming area;

a first well layer of a first conductivity type formed in the digital circuit forming area;

a second well layer of the first conductivity type formed in the analog circuit forming area;

a non-doped film formed on a surface of the second well layer;

a first gate insulating film formed on a surface of the first well layer;

a second gate insulating film formed on a surface of the non-doped film;

a first gate electrode formed on a surface of the first gate insulating film;

a second gate electrode formed on a surface of the second gate insulating film;

sidewalls formed of insulating films on side surfaces of respective ones of the first gate electrode and the second gate electrode;

a first source region and a first drain region of a second conductivity type formed in the first well layer with the first gate electrode interposed therebetween;

a second source region and a second drain region of the second conductivity type formed in the non-doped film and the second well layer with the second gate electrode interposed therebetween; and

silicide films formed on surfaces of the first source region, the first drain region, and the first gate electrode and the second source region, the second drain region, and the second gate electrode.