GATE CUT METHOD

• US 20180277440A1
• Filed: 03/23/2017
• Published: 09/27/2018
• Est. Priority Date: 03/23/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: YU, Hong, HU, Zhenyu, WANG, Haiting
• Granted Patent: US 10,083,874 B1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a sacrificial gate layer over a plurality of semiconductor fins;

etching the sacrificial gate layer in a first etching step to form a gate cut opening that extends through the sacrificial gate layer, wherein the gate cut opening is located between an adjacent pair of the fins;

forming a spacer layer on sidewalls of the gate cut opening; and

etching the sacrificial gate layer in a second etching step after the first etching step to form a first sacrificial gate structure that overlies a first one of the pair of adjacent fins and a second sacrificial gate structure that overlies a second one of the pair of adjacent fins.

2. The method of claim 1, wherein the gate cut opening extends completely through the sacrificial gate layer.

3. The method of claim 1, wherein the sacrificial gate layer comprises amorphous silicon.

4. The method of claim 1, wherein the gate cut opening has at least one lateral dimension ranging from 30 to 40 nm.

6. The method of claim 1, wherein the spacer layer comprises amorphous silicon.

7. The method of claim 1, wherein the gate cut opening after forming the spacer layer has at least one lateral dimension ranging from 10 to 20 nm.

8. The method of claim 1, further comprising filling the gate cut opening prior to the second etching step.

9. The method of claim 1, wherein a distance between the first sacrificial gate structure and the second sacrificial gate structure is 10 to 20 nm.

10. The method of claim 9, wherein the distance between the first sacrificial gate structure and the second sacrificial gate structure is measured in a direction orthogonal to a length direction of the fins.

11. The method of claim 1, wherein the first etching step and the second etching step each comprise an anisotropic etch.

12. The method of claim 1, further comprising forming a dielectric layer between the first sacrificial gate structure and the second sacrificial gate structure.

13. The method of claim 1, wherein the gate cut opening has substantially vertical sidewalls.

5. (canceled)

14. A method of forming a semiconductor structure, comprising:

forming a sacrificial gate layer over a plurality of semiconductor fins;

etching the sacrificial gate layer in a first etching step to form a gate cut opening located between an adjacent pair of the fins;

forming a spacer layer on sidewalls of the gate cut opening;

depositing a fill layer within the gate cut opening to fill the gate cut opening;

forming a patterned hard mask over the sacrificial gate layer; and

using the patterned hard mask as an etch mask, etching the sacrificial gate layer to form a first sacrificial gate structure that overlies a first one of the pair of adjacent fins and a second sacrificial gate structure that overlies a second one of the pair of adjacent fins, wherein forming the gate cut opening precedes forming the first and second sacrificial gate structures.

15. The method of claim 14, wherein the sacrificial gate layer and the spacer layer each comprise amorphous silicon.

16. The method of claim 14, wherein the first etching step and the second etching step each comprise reactive ion etching.

17. The method of claim 14, further comprising forming a dielectric layer between the first sacrificial gate structure and the second sacrificial gate structure.

18. The method of claim 14, wherein the gate cut opening has substantially vertical sidewalls.

19. A method of forming a semiconductor structure, comprising:

forming a sacrificial gate layer over a plurality of semiconductor fins;

etching the sacrificial gate layer in a first etching step to form a gate cut opening that extends through the sacrificial gate layer, wherein the gate cut opening is located between an adjacent pair of the fins;

filling the gate cut opening; and

etching the sacrificial gate layer in a second etching step after the first etching step to form a first sacrificial gate structure that overlies a first one of the pair of adjacent fins and a second sacrificial gate structure that overlies a second one of the pair of adjacent fins, wherein the gate cut opening is filled prior to the second etching step.