NORMALLY OFF III NITRIDE TRANSISTOR

• US 20180277535A1
• Filed: 05/24/2018
• Published: 09/27/2018
• Est. Priority Date: 03/30/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Fareed, Qhalid, Tipirneni, Naveen
• Granted Patent: US 11,011,515 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02241 III-V semiconductor
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Claims

1. A method of forming a semiconductor device, comprising the steps:

forming a low-doped layer of III-N material over a substrate, in an area for an enhancement mode GaN FET;

forming a barrier layer of III-N material by a metal-organic chemical vapor deposition (MOCVD) process over the low-doped layer, the barrier layer having less than 1 atomic percent indium;

forming a stressor layer of III-N material by an MOCVD process over the barrier layer, the stressor layer having a stoichiometry of In_0.05Al_0.95N to In_0.30Al_0.70N, and a thickness of 1 nanometers to 5 nanometers;

forming a cap layer of III-N material by an MOCVD process over the stressor layer;

forming a recess mask over the cap layer which exposes an area for a gate recess in the area for the enhancement mode GaN FET;

removing the cap layer in the area exposed by the recess mask by a first etch process to form a portion of a gate recess of the enhancement mode GaN FET, the first etch process leaving at least a portion of the stressor layer under the area exposed by the recess mask;

removing the stressor layer in the area exposed by the recess mask by a second etch process to form the gate recess, the second etch process having a different chemistry than the first etch process, the second etch process leaving at least a portion of the barrier layer under the gate recess;

forming a gate dielectric layer over the barrier layer in the gate recess; and

forming a gate of the enhancement mode GaN FET over the gate dielectric layer in the gate recess.

2. The method of claim 1, wherein the substrate is a 150 millimeter wafer, and forming the barrier layer comprises:

placing the substrate on a susceptor in an MOCVD chamber;

heating the susceptor to a temperature of 900°

C. to 1100°

C.;

flowing hydrogen gas into the MOCVD chamber at a flow rate of 80 standard liters per minute (slm) to 120 slm;

flowing a nitrogen source into the MOCVD chamber at a flow rate of 5 slm to 30 slm;

flowing an aluminum precursor into the MOCVD chamber at a rate of 80 standard cubic centimeters per minute (sccm) to 130 sccm;

flowing a gallium precursor into the MOCVD chamber at a rate of 40 sccm to 160 sccm; and

maintaining a pressure in the MOCVD chamber at 50 torr to 200 torr.

3. The method of claim 1, wherein the substrate is a 150 millimeter wafer, and forming the stressor layer comprises:

placing the substrate on a susceptor in an MOCVD chamber;

heating the susceptor to a temperature of 700°

C. to 850°

C.;

flowing nitrogen gas into the MOCVD chamber at a flow rate of 60 slm to 100 slm;

flowing a nitrogen source into the MOCVD chamber at a flow rate 5 slm to 40 slm;

flowing an aluminum precursor into the MOCVD chamber at a rate of 80 sccm to 130 sccm;

flowing a indium precursor into the MOCVD chamber at a rate 100 sccm to 300 sccm; and

maintaining a pressure in the MOCVD chamber at 100 torr to 400 torr.

4. The method of claim 1, wherein the substrate is a 150 millimeter wafer, and forming the cap layer comprises:

placing the substrate on a susceptor in an MOCVD chamber;

heating the susceptor to a temperature of 750°

C. to 900°

C.;

flowing nitrogen gas into the MOCVD chamber at a flow rate of 80 slm to 120 slm;

flowing a nitrogen source into the MOCVD chamber at a flow rate of 5 slm to 35 slm;

flowing an aluminum precursor into the MOCVD chamber at a rate of 80 sccm to 130 sccm;

flowing a gallium precursor into the MOCVD chamber at a rate of 40 sccm to 60 sccm; and

maintaining a pressure in the MOCVD chamber at 50 torr to 200 torr.

5. The method of claim 1, wherein the barrier layer, the stressor layer and the cap layer are formed in one MOCVD chamber.

6. The method of claim 1, wherein the first etch process comprises a plasma etch process with chlorine radicals.

7. The method of claim 1, wherein the second etch process comprises a wet etch process with an aqueous solution of 1,2 diaminoethane.

8. The method of claim 1, comprising oxidizing the stressor layer in the area exposed by the recess mask to form an oxidized stressor layer, after removing the cap layer in the area exposed by the recess mask, wherein the second etch process removes the oxidized stressor layer.

9. The method of claim 1, comprising oxidizing a remaining portion of the stressor layer left in the area exposed by the recess mask after the step of removing the stressor layer by the first etch process.

10. The method of claim 1, wherein the gate dielectric layer extends over the cap layer, the stressor layer and the barrier layer in an area for a gate of a depletion mode GaN FET of the semiconductor device.

11. The method of claim 10, wherein forming the gate of the enhancement mode GaN FET comprises:

forming a layer of gate material over the gate dielectric layer in the gate recess and in the area for the gate of the depletion mode GaN FET; and

forming the gate of the enhancement mode GaN FET concurrently with the gate of the depletion mode GaN FET from the layer of gate material.

12. A method of forming a semiconductor device, comprising the steps:

forming a first layer of III-N material over a substrate, in an area for an enhancement mode GaN FET;

forming a second layer of III-N material by a metal-organic chemical vapor deposition (MOCVD) process over the first layer, the second layer having less than 1 atomic percent indium;

forming a third layer of III-N material by an MOCVD process over the second layer, the third layer having a stoichiometry of In_0.05Al_0.95N to In_0.30Al_0.70N, and a thickness of 1 nanometers to 5 nanometers;

forming a fourth layer of III-N material by an MOCVD process over the third layer;

forming a recess mask over the fourth layer which exposes an area for a gate recess in the area for the enhancement mode GaN FET;

removing the fourth layer in the area exposed by the recess mask by a first etch process to form a portion of a gate recess of the enhancement mode GaN FET, the first etch process leaving at least a portion of the third layer under the area exposed by the recess mask;

removing the third layer in the area exposed by the recess mask by a second etch process to form the gate recess, the second etch process having a different chemistry than the first etch process, the second etch process leaving at least a portion of the second layer under the gate recess;

forming a gate dielectric layer over the second layer in the gate recess; and

forming a gate of the enhancement mode GaN FET over the gate dielectric layer in the gate recess.

13. The method of claim 12, wherein the second layer, the third layer and the fourth layer are formed in one MOCVD chamber.

14. The method of claim 12, wherein the first etch process comprises a plasma etch process with chlorine radicals.

15. The method of claim 12, wherein the second etch process comprises a wet etch process with an aqueous solution of 1,2 diaminoethane.

16. The method of claim 12, comprising oxidizing the third layer in the area exposed by the recess mask to form an oxidized third layer, after removing the fourth layer in the area exposed by the recess mask, wherein the second etch process removes the oxidized third layer.

17. The method of claim 12, comprising oxidizing a remaining portion of the third layer left in the area exposed by the recess mask after the step of removing the third layer by the first etch process.

18. The method of claim 12, wherein the gate dielectric layer extends over the fourth layer, the third layer and the second layer in an area for a gate of a depletion mode GaN FET of the semiconductor device.