SUMMATION FOR MULTI-CHANNEL PHOTOMULTIPLIER ARRAY SIGNALS

• US 20180283938A1
• Filed: 09/29/2016
• Published: 10/04/2018
• Est. Priority Date: 10/02/2015
• Status: Active Grant

• Current Assignee: Universitat de Barcelona (University of Barcelona)
• Original Assignee: Universitat de Barcelona (University of Barcelona)
• Inventors: GASCON FORA, David, GOMEZ FERNANDEZ, Sergio, MAURICIO FERRE, Joan
• Granted Patent: US 10,605,656 B2
• Time in Patent Office: Days
• CPC Class Codes: G01J 1/44 Electric circuits for command of an exposure part G03B7/02
• CPC Class Codes: G01J 2001/4413 Type
• CPC Class Codes: G01J 2001/4446 Type of detector
• CPC Class Codes: G05F 3/26 Current mirrors
• CPC Class Codes: G05F 3/265 using bipolar transistors only
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

A summation circuit (1) for summing one or more signals received from a photomultiplier array is proposed. The summation circuit comprises one or more readout circuits (5) coupleable to one or more photodiodes of the photomultiplier array (2), respectively, and a channel summing module (50), coupled at one or more outputs of the one or more readout circuits, respectively, to sum the one or more signals provided by the one or more readout circuits. The one or more readout circuits are coupleable to the photodiode of the photomultiplier array. Each readout circuit (5) comprises one or more coefficient controllers (C1, C2) for controlling multiplying coefficients of the received signal. The coefficient controllers may be placed at the input and/or at the output of the readout circuits (5).

Claims

1. A summation circuit (1) for summing two or more signals received from a photomultiplier array, comprising:

two or more readout circuits (5) coupleable to two or more photodiodes (3) of the photomultiplier array respectively, and

a channel summing module (50), coupled at one or more outputs of the readout circuits, respectively, configured to sum the two or more signals provided by the readout circuits,

each readout circuit (5) comprising;

one or more coefficient controllers (C1, C2) for controlling multiplying coefficients of the received signal; and

at least one channel circuit (7), coupled to the one or more coefficient controllers, the channel circuit comprising;

a first resistor (Rd), coupleable at one end to the anode of the photodiode, and

an input stage (15), coupled to the other end of the first resistor, the input stage comprising;

a current mirror configuration (20) having at least a first gain path, wherein the first gain path comprises;

an input branch (22) with at least one input amplifier, and

a first output branch (25) with at least one mirror amplifier having its base and emitter connected to the base and emitter of the input amplifier of the input branch; and

a feedback circuit (40) arranged between the base of the input amplifier and the input of the current mirror configuration,

wherein the one or more coefficient controllers comprises a current switch (CS) coupled to the output of the at least one channel circuit,

wherein the current switch (CS) comprises one or more common base transistors (QCB0-QCBm) and an Operational Transconductance Amplifier (OTA2), wherein a noninverting input of the OTA2 is coupled the anode reference voltage, an inverting input of the OTA2 is coupled to the input of the current switch and an output of the OTA2 is coupled to one or more selectors, each of the one or more selectors being coupled to one of the one or more bases of the one or more common base transistors, respectively.

2. The summation circuit according to claim 1, wherein the one or more coefficient controllers comprises an anode voltage controller (C1), coupled between the anode of the photodiode and the first resistor (Rd) of the channel circuit.

3. The summation circuit according to claim 2, wherein the anode voltage controller comprises:

an inverter, having an input and an output;

a first FET (Mo1), having a collector coupled to a reference voltage, an emitter coupled to the anode of the at least one photodiode and a base coupled to the output of the inverter;

a second FET (Mo2), having a collector coupled to the first resistor (Rd), an emitter coupled to the anode of the at least one photodiode and a base coupled to the input of the inverter.

6. The summation circuit according to any of claims 1 to 5, wherein

the channel summing module comprises one or more summing elements, each summing element having a saturation control element and one or more resistors coupled in a parallel configuration.

7. The summation circuit according to claim 6, wherein the saturation control element comprises a summing amplifier having a collector and a base coupled to the power supply and an emitter coupled to the one or more outputs of the readout circuit.

8. The summation circuit according to claim 6 or 7, wherein the one or more resistors are selectable to control an overall multiplying coefficient of a summation result.

9. The summation circuit according to any of claims 1 to 8, wherein the feedback circuit (40) comprises a high frequency feedback circuit comprising at least a first amplifier (Qf) and a second amplifier (Mf),

the first amplifier (Qf) having a collector coupled to a power supply voltage (Vdd), a base coupled to a collector of the second amplifier (Mf) and an emitter coupled to the base of the input amplifier and to earth via a current source,

the second amplifier (Mf) having a base coupled to earth via a first capacitor and an emitter coupled to the input of the current mirror configuration.

10. The summation circuit according to claim 9, wherein the feedback circuit (40) further comprises a low frequency feedback circuit (60) coupled between the base of the second amplifier (Mf) and the input of the input branch.

11. The summation circuit according to claim 10, wherein the low frequency feedback circuit comprises an Operational Transconductance Amplifier (OTA) (65) having a positive input coupled to a voltage supply reference, a negative input coupled to the input of the input branch and an output coupled to the base of the second amplifier (Mf).

12. The summation circuit according to any of claims 1 to 11, wherein the summation circuit is configured to receive signals from a silicon photomultiplier array (SiPM).

4. A summation circuit (1) for summing two or more signals received from a photomultiplier array, comprising:

two or more readout circuits (5) coupleable to two or more photodiodes (3) of the photomultiplier array respectively, and

a channel summing module (50), coupled at one or more outputs of the readout circuits, respectively, configured to sum the two or more signals provided by the readout circuits,

each readout circuit (5) comprising;

one or more coefficient controllers (C1, C2) for controlling multiplying coefficients of the received signal; and

at least one channel circuit (7), coupled to the one or more coefficient controllers, the channel circuit comprising;

a first resistor (Rd), coupleable at one end to the anode of the photodiode, and

an input stage (15), coupled to the other end of the first resistor, the input stage comprising;

a current mirror configuration (20) having at least a first gain path, wherein the first gain path comprises;

an input branch (22) with at least one input amplifier, and

a first output branch (25) with at least one mirror amplifier having its base and emitter connected to the base and emitter of the input amplifier of the input branch; and

a feedback circuit (40) arranged between the base of the input amplifier and the input of the current mirror configuration,

wherein the one or more coefficient controllers comprises an anode voltage controller (C1), coupled between the anode of the photodiode and the first resistor (Rd) of the channel circuit.

5. The summation circuit according to claim 4, wherein the anode voltage controller comprises:

an inverter, having an input and an output;

a first FET (Mo1), having a collector coupled to a reference voltage, an emitter coupled to the anode of the at least one photodiode and a base coupled to the output of the inverter;

a second FET (Mo2), having a collector coupled to the first resistor (Rd), an emitter coupled to the anode of the at least one photodiode and a base coupled to the input of the inverter.