MULTI-CHIP PACKAGE WITH SELECTION LOGIC AND DEBUG PORTS FOR TESTING INTER-CHIP COMMUNICATIONS

• US 20180284186A1
• Filed: 04/28/2017
• Published: 10/04/2018
• Est. Priority Date: 04/03/2017
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: CHADHA, Ish, BLOEMER, Robert
• Granted Patent: US 10,317,459 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA

Abstract

A microelectronic package has an IC chip that includes logical circuitry for routing certain I/O signals to debug ports disposed on an outer surface of the microelectronic package. The I/O signals include data and command signals that are transmitted between semiconductor chips in the microelectronic package via conductive traces that are not physically accessible via with conventional debugging techniques. The logical circuitry may be configured to programmably select I/O signals based on a software input, and may be connected to the various I/O signals transmitted between the IC chip and another IC chip in the microelectronic package when a debugging of the I/O signals is enabled. Circuitry employed in conventional operation of the IC chip may also be employed to connect the logical circuitry to the various I/O signals.

Claims

1. A microelectronic package, comprising:

a plurality of debug ports formed on an outer surface of the microelectronic package;

a first semiconductor chip that is coupled to a semiconductor interposer and includes;

a first plurality of electrical contacts, wherein each electrical contact included in the first plurality of electrical contacts is electrically coupled to a respective electrically conductive trace formed within the semiconductor interposer, and

logical circuitry that selects a set of electrical contacts from the plurality of electrical contacts and electrically couples each electrical contact in the set of electrical contacts to a respective debug port in the plurality of debug ports; and

a second semiconductor chip that is coupled to the semiconductor interposer and includes a second plurality of electrical contacts, wherein each electrical contact included in the second plurality of electrical contacts is electrically coupled to one of the electrically conductive traces formed within the semiconductor interposer.

2. The microelectronic package of claim 1, further comprising a third semiconductor chip that is disposed on the second semiconductor chip such that the second semiconductor chip resides between the semiconductor interposer and the third semiconductor chip.

3. The microelectronic package of claim 2, wherein the third semiconductor chip includes a third plurality of electrical contacts, wherein each electrical contact in the third plurality of electrical contacts is electrically coupled to the first semiconductor chip via one of the electrically conductive traces formed within the semiconductor interposer.

4. The microelectronic package of claim 3, wherein the logical circuitry is configured to electrically couple at least one electrical contact included in the third plurality of electrical contacts to a debug port included in the plurality of debug ports.

5. The microelectronic package of claim 1, wherein the plurality of debug ports includes a subset of N debug ports, and the logical circuitry selects a set of N electrical contacts from the second plurality of electrical contacts and electrically couples each electrical contact in the set of N electrical contacts to a respective debug port included in the subset of N debug ports, wherein N is a positive integer.

6. The microelectronic package of claim 1, wherein the logical circuitry is programmable to select the set of electrical contacts from the plurality of electrical contacts based on a software input.

7. The microelectronic package of claim 1, wherein the logical circuitry electrically couples at least one electrical contact included in the second plurality of electrical contacts to a debug port included in the plurality of debug ports.

8. The microelectronic package of claim 1, wherein the logical circuitry selects the set of electrical contacts from the first plurality of electrical contacts in response to a debug bus enable signal.

9. The microelectronic package of claim 1, wherein at least one debug port included in the plurality of debug ports is formed on a surface of a printed circuit board coupled to the microelectronic package.

10. The microelectronic package of claim 1, wherein at least one debug port included in the plurality of debug ports is formed on a surface of a package substrate that is coupled to the interposer.

11. The microelectronic package of claim 1, wherein each electrical contact included in the first plurality of electrical contacts is electrically coupled to a respective conductive trace in the first semiconductor chip that connects an output of a respective transmitter in the first semiconductor chip to an input of a respective receiver in the second semiconductor chip, and wherein the respective receiver is coupled to the logical circuitry.

12. The microelectronic package of claim 11, wherein each respective receiver is coupled to the logical circuitry via a respective selectable logic device.

13. The microelectronic package of claim 12, wherein the respective selectable logic device couples the respective receiver to the logical circuitry in response to a debug bus enable signal.

14. The microelectronic package of claim 1, wherein each electrical contact included in the second plurality of electrical contacts is electrically coupled to a respective conductive trace in the first semiconductor chip that connects to an input of a respective receiver in the first semiconductor chip, and wherein the respective receiver is coupled to the logical circuitry.

15. A method for testing connections between a first semiconductor chip and a second semiconductor chip within a microelectronic package, the method comprising:

causing a signal to be transmitted between the first semiconductor chip and the second semiconductor chip via a conductive trace formed within a semiconductor interposer and an electrical contact in a plurality of electrical contacts included in the first semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip are both coupled to a surface of the interposer; and

routing the signal to a debug port that is disposed on an outer surface of the microelectronic package.

16. The method of claim 15, further comprising:

receiving a software input indicating the signal; and

routing the signal to the debug port in response to receiving the software input.

17. The method of claim 15, further comprising:

causing a group of N signals to be sent between the first semiconductor chip to the second semiconductor chip, wherein each signal in the group of N signals is sent via a respective electrical contact in the plurality of electrical contacts and a respective conductive trace within the semiconductor interposer; and

routing each signal in the group of N signals to a respective debug port that is disposed on the outer surface of the microelectronic package.

18. The method of claim 17, wherein the group of N signals includes at least one clock signal from the first semiconductor chip, at least one command signal from the first semiconductor chip to the second semiconductor chip, at least one reset signal, and at least one data signal either from the first semiconductor chip to the second semiconductor chip or from the second semiconductor chip to the first semiconductor chip.

19. The method of claim 15, wherein routing the signal to the debug port comprises routing the signal to the debug port via a conductive trace disposed entirely within the first semiconductor chip.

20. The method of claim 15, further comprising:

causing an additional signal to be sent between the second semiconductor chip to the first semiconductor chip via an additional conductive trace formed within the semiconductor interposer and an additional electrical contact in the plurality of electrical contacts included in the first semiconductor chip; and

routing the signal from the additional electrical contact to an additional debug port that is disposed on an outer surface of the microelectronic package.

21. A microelectronic package, comprising:

a plurality of debug ports formed on an outer surface of the microelectronic package;

a first semiconductor chip that is coupled to a semiconductor interposer and includes;

a first plurality of electrical contacts, wherein each electrical contact is electrically coupled to a respective electrically conductive trace formed within the semiconductor interposer, and

logical circuitry configured to select a set of electrical contacts from the plurality of electrical contacts and to electrically couple each electrical contact in the set of electrical contacts to a respective debug port in the plurality of debug ports; and

a second semiconductor chip that is coupled to the semiconductor interposer and includes a second plurality of electrical contacts,

wherein each electrical contact in the second plurality of electrical contacts is electrically coupled to a conductive trace of the first semiconductor chip,

wherein the conductive trace of the first semiconductor chip connects an output of a transmitter included in the first semiconductor chip to an input of a receiver that also is included in the first semiconductor chip and is coupled to the logical circuitry, and

wherein the transmitter is configured to transmit a signal to the second semiconductor chip, and the receiver is configured to receive a signal from the second semiconductor chip.