REGISTER SPILL/FILL USING SHARED LOCAL MEMORY SPACE

• US 20180285120A1
• Filed: 04/01/2017
• Published: 10/04/2018
• Est. Priority Date: 04/01/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Arthur D. Hunter Jr
• Inventors: Ray, Joydeep, Koker, Altug, Vembu, Balaji, Ramadoss, Murali, Lueh, Guei-Yuan, Valerio, James A., Surti, Prasoonkumar, Appu, Abhishek R., Ranganathan, Vasanth, Bhairavabhatla, Kalyan, Hunter, JR., Arthur D., Chen, Wei-Yu, Maiyuran, Subramaniam M.
• Granted Patent: US 10,453,427 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/455 Image or video data
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2350/00 Solving problems of bandwidth in display systems
• CPC Class Codes: G09G 2352/00 Parallel handling of streams of display data
• CPC Class Codes: G09G 2360/08 Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A mechanism is described for facilitating using of a shared local memory for register spilling/filling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

Claims

1. An apparatus comprising:

reservation/execution logic to reserve one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor.

2. The apparatus of claim 1, wherein the reservation and execution logic is further to execute the one or more of the spilling and the filling relating to the registers using the one or more spaces in the shared local memory.

3. The apparatus of claim 1, further comprising computing/holding logic to load and hold one or more constants in the one or more spaces of the SLM.

4. The apparatus of claim 1, further comprising detection/generation logic to facilitate a compiler to detect the registers and generate a code to specify the one or more spaces of the SLM needed for the one or more of the spilling and filling relating to the registers.

5. The apparatus of claim 4, wherein the compiler, as facilitated by the computing/holding logic, is further to compute the one or more spaces determined to be necessary for the one or more of the spilling and filling relating to the registers.

6. The apparatus of claim 4, further comprising communication/compatibility logic to facilitate the compiler to communicate the code specifying the one or more spaces of the SLM to a graphics driver associated with the graphics processor, wherein the communication/compatibility logic is further to facilitate the graphics driver to communicate information relating to the one or more spaces of the SLM to the graphics processor.

7. The apparatus of claim 1, wherein the graphics processor is co-located with an application processor on a common semiconductor package.

8. A method comprising:

reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

9. The method of claim 8, further comprising executing the one or more of the spilling and the filling relating to the registers using the one or more spaces in the shared local memory.

10. The method of claim 8, further comprising loading and holding one or more constants in the one or more spaces of the SLM.

11. The method of claim 8, further comprising facilitating a compiler to detect the registers and generate a code to specify the one or more spaces of the SLM needed for the one or more of the spilling and filling relating to the registers.

12. The method of claim 11, wherein the compiler is further to compute the one or more spaces determined to be necessary for the one or more of the spilling and filling relating to the registers.

13. The method of claim 11, further comprising facilitating the compiler to communicate the code specifying the one or more spaces of the SLM to a graphics driver associated with the graphics processor, wherein the graphics driver to communicate information relating to the one or more spaces of the SLM to the graphics processor.

14. The method of claim 8, wherein the graphics processor is co-located with an application processor on a common semiconductor package.

15. At least one machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:

reserving one or more spaces of a shared local memory (SLM) to perform one or more of spilling and filling relating to registers associated with a graphics processor of a computing device.

16. The machine-readable medium of claim 15, wherein the operations further comprise execute the one or more of the spilling and the filling relating to the registers using the one or more spaces in the shared local memory.

17. The machine-readable medium of claim 15, wherein the operations further comprise load and hold one or more constants in the one or more spaces of the SLM.

18. The machine-readable medium of claim 15, wherein the operations further comprise facilitate a compiler to detect the registers and generate a code to specify the one or more spaces of the SLM needed for the one or more of the spilling and filling relating to the registers.

19. The machine-readable medium of claim 18, wherein the compiler is further to compute the one or more spaces determined to be necessary for the one or more of the spilling and filling relating to the registers.

20. The machine-readable medium of claim 18, wherein the operations further comprise facilitate the compiler to communicate the code specifying the one or more spaces of the SLM to a graphics driver associated with the graphics processor, wherein the graphics driver to communicate information relating to the one or more spaces of the SLM to the graphics processor, wherein the graphics processor is co-located with an application processor on a common semiconductor package.