MEMORY SYSTEM, READING METHOD THEREOF AND WRITING METHOD THEREOF

• US 20180285185A1
• Filed: 03/29/2017
• Published: 10/04/2018
• Est. Priority Date: 03/29/2017
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Wang, Shih-Chung
• Granted Patent: US 10,545,805 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1088 Reconstruction on already foreseen single or plurality of spare disks
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

A memory system, a reading method and a writing method are provided. The memory system includes a memory controller and a memory array electrically connected to the memory controller. A parity information is stored in the memory array. The memory array includes a plurality of memory devices. The reading method comprises the following steps: A reading command for requesting a user data stored in the memory array is received from a host interface. The user data is recovered according to the parity information when the user data is error at one of the memory devices. The user data, which is recovered, is transferred to the host interface and the user data is refreshed.

Claims

1. A reading method of a memory system, wherein the memory system includes a memory controller and a memory array electrically connected to the memory controller, a parity information is stored in the memory array, the memory array includes a plurality of memory devices, and the reading method comprises:

receiving a reading command for requesting a user data stored in the memory array from a host interface;

recovering the user data according to the parity information when the user data is error at one of the memory devices; and

transferring the user data, which is recovered, to the host interface and refreshing the user data.

2. The reading method of the memory system according to claim 1, further comprising:

recording an identifier of the memory device whose user data is error into a refresh list of a control table which is stored in the memory array.

3. The reading method of the memory system according to claim 2, further comprising:

removing the identifier from the refresh list when the user data is refreshed.

4. The reading method of the memory system according to claim 1, further comprising:

recording an identifier of the memory device which is executed a heating repair operation into a heating repair list of a control table which is stored in the memory array.

5. The reading method of the memory system according to claim 4, further comprising:

removing the identifier of the memory device from the heating repair list when the heating repair operation is finished.

6. The reading method of the memory system according to claim 1, further comprising:

transferring the user data, which is recovered, to the host interface and executing a search read operation when a heating repair operation is executed.

7. A writing method of a memory system, wherein the memory system includes a memory controller and a memory array electrically connected to the memory controller, a parity information is stored in the memory array, the memory array includes a plurality of memory devices, and the writing method comprises:

receiving a writing command for writing a user data into the memory array;

allocating a plurality of pages of the memory array to store the user data;

if one of the pages being allocated is unavailable to be accessed at one of the memory devices, storing the user data and the parity information corresponding the user data in the pages being allocated except the memory device which is unavailable to be accessed;

executing a heating repair operation on the memory device which is unavailable to be accessed; and

restoring the user data to the memory array after the heating repair operation is finished.

8. The writing method of the memory system according to claim 7, further comprising:

recording an identifier of the memory device which is executed the heating repair operation into a heating repair list of a control table which is stored in the memory array.

9. The writing method of the memory system according to claim 8, further comprising:

moving the identifier of the memory device from the heating repair list to a store list when the heating repair operation is finished.

10. The writing method of the memory system according to claim 9, further comprising:

removing the identifier of the memory device from the store list when the user data is restored.

11. The writing method of the memory system according to claim 7, further comprising:

determining whether there is any other of the memory devices needed to be executed the heating repair operation.

12. The writing method of the memory system according to claim 11, wherein whether there is any other of the memory devices needed to be executed the heating repair operation is determined according to an erasing count.

13. A memory system, comprising:

a memory controller; and

a memory array, including a plurality of memory devices, wherein a control table are stored in the memory array;

wherein the control table includes a refresh list, and when a user data is error at one of the memory devices, a first identifier of one of the memory devices whose user data is error is recorded into the refresh list.

14. The memory system according to claim 13, wherein the control table further includes a heating repair list, and when the user data is unavailable to be accessed at one of the memory devices, a second identifier of one of the memory devices which is unavailable to be accessed is recorded into the heating repairing list.

15. The memory system according to claim 14, wherein the control table further includes a restore list, and when a heating repair operation executed on the memory device which is unavailable to be accessed is finished, the second identifier recorded in the heating repair list is moved to the restore list.