GARBAGE COLLECTION

• US 20180285258A1
• Filed: 04/04/2017
• Published: 10/04/2018
• Est. Priority Date: 04/04/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Muchherla, Kishore K., Ratnam, Sampath K., Feeley, Peter, Miller, Michael G., Hubbard, Daniel J., Padilla, Renato C., Malshe, Ashutosh, Singidi, Harish R.
• Granted Patent: US 10,380,018 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Claims

1. An apparatus, comprising:

a memory comprising a plurality of mixed mode blocks;

a controller configured to;

write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode; and

write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode;

wherein writing the second portion of sequential host data includes performing a garbage collection operation that includes adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

2. The apparatus of claim 1, wherein the controller configured to perform the garbage collection operation comprises the controller configured to perform a garbage collection operation that results in at least half of the plurality of mixed mode blocks being logically sequential.

3. The apparatus of claim 1, wherein the controller is configured to garbage collect the first portion of sequential host data by garbage collecting a first set of data stored in a first block of the plurality of mixed mode blocks and a second set of data stored in a second block of the plurality of mixed mode blocks and writing the first set and the second set to the first block.

4. The apparatus of claim 3, wherein the first set of data and the second set of data are logically sequential in relation to each other.

5. The apparatus of claim 3, wherein the controller is further configured to write a third set of host data to the first block, wherein the first block stores the first set, the second set, and the third set.

6. The apparatus of claim 5, wherein the third set is not logically sequential in relation to the first set and the second set.

7. The apparatus of claim 6, wherein the first block storing the first set, the second set, and the third set is a logically fragmented block.

8. The apparatus of claim 5, wherein the controller is further configured to write a fourth set of host data to the second block.

9. The apparatus of claim 8, wherein the second block storing the fourth set is logically sequential.

10. The apparatus of claim 8, wherein the fourth set comprises three data units and wherein the three data units are logically sequential in relation to each other.

11. A method, comprising:

writing a first portion of host data to a plurality of mixed mode blocks of a memory in a single level cell (SLC) mode;

writing a second portion of host data to the plurality of mixed mode blocks in an extra level cell (XLC) mode;

wherein writing the second portion of host data comprises performing a garbage collection operation that includes folding at least two data units of the first portion into a same block as at least one data unit of the second portion.

12. The method of claim 11, comprising writing a third portion of host data in an XLC mode to a block that previously stored one of the at least two data units of the first portion.

13. The method of claim 11, wherein the at least two data units of the first portion are each stored in a different block of memory.

14. The method of claim 11, wherein writing the second portion of data comprises, in response to a threshold number of blocks being empty, garbage collecting a first block and a second block stored in an SLC mode to be stored in the first block in an XLC mode.

15. The method of claim 14, wherein writing the second portion of data comprises writing host data to the second block, wherein the garbage collection operation was triggered in response to the host data being sent when there was the threshold number of empty blocks.

16. An apparatus, comprising:

a memory comprising a plurality of mixed mode blocks;

a controller configured to;

write sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode; and

perform a garbage collection operation on a portion of data of the sequential host data stored in at least one of the plurality of mixed mode blocks and store the portion of data in an XLC mode in response to a threshold quantity of the plurality of mixed mode blocks storing valid data.

17. The apparatus of claim 16, wherein the controller is configured to determine the garbage collection operation should be performed on the portion of data based on a determination of an amount of valid data in each of the plurality of mixed mode blocks.

18. The apparatus of claim 16, wherein the controller is configured to determine which set of data of the sequential host data to perform the garbage collection operation based on a determination of whether a particular block is an SLC mode block.

19. The apparatus of claim 18, wherein the controller is configured to determine which block is the particular block based on whether the particular block includes an amount of valid data.

20. The apparatus of claim 18, wherein the controller is configured to, in response to a determination that the particular block is an XLC mode block, determine whether a next least valid block with a next most amount of invalid data is an XLC mode block.

21. The apparatus of claim 20, wherein the controller is configured to, in response to determining that the next least valid block is an XLC mode block, choose the particular block to perform the garbage collection on.

22. The apparatus of claim 20, wherein the controller is configured to, in response to determining that the next least valid block is an SLC mode block, choose the next least valid to perform the garbage collection on.

23. A method, comprising:

writing sequential host data to a plurality of mixed mode blocks of a memory in a single level cell (SLC) mode;

in response to a quantity of blocks of the plurality of mixed mode blocks that are capable of being written to reaching a threshold quantity, performing a garbage collection operation on at least one of the plurality of mixed mode blocks;

wherein the at least one of the plurality of mixed mode blocks is chosen for performing the garbage collection operation based on an amount of valid data associated with each of the plurality of mixed mode blocks.

24. The method of claim 23, wherein the at least one of the plurality of mixed mode blocks is chosen based on whether the at least one of the plurality of mixed mode blocks is in an SLC mode.

25. The method of claim 23, wherein the at least one of the plurality of mixed mode blocks is chosen based on, in response to a block with a highest quantity of invalid data being an XLC mode block, determining whether a next-most highest invalid data block is an SLC mode block.

26. The method of claim 25, wherein the highest quantity of invalid data block is chosen in response to the next-most highest invalid data block being in an XLC mode.

27. The method of claim 25, wherein the next-most highest invalid data block is chosen in response to the next-most highest invalid data block being an SLC mode block.