CONTEXT-SENSITIVE INTERRUPTS

• US 20180285291A1
• Filed: 03/31/2017
• Published: 10/04/2018
• Est. Priority Date: 03/31/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Steffen Schulz
• Inventors: Schulz, Steffen, Koeberl, Patrick, Shanbhogue, Vedvyas, Brandt, Jason W., Madduri, Venkateswara R., Kim, Sang W., Carreno, Julien
• Granted Patent: US 10,496,573 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

Methods, apparatus, and system to create interrupts which are resolved at runtime relative to an active compartment. Active compartments may be, for example, a compartment of an operating system (“OS”) or a trusted execution environment (“TEE”). The context-specific interrupts comprise an interrupt dispatch table (“IDT”) for each compartment.

Claims

1. An apparatus for computing, comprising:

a computer processor, a memory, and a hardware exception unit; and

a context-sensitive interrupt instantiation module to instantiate an interrupt of a process executed by the computer processor in a compartment, wherein to instantiate the interrupt, the context-sensitive interrupt instantiation module is to create an interrupt gate entry in an interrupt dispatch table (“

IDT”

), wherein the interrupt gate entry is to be resolved at runtime according to a then-active compartment, independent of other compartments, to trigger the interrupt and interrupt the process upon detection of an interrupt signal by the hardware exception unit.

2. The apparatus according to claim 1, wherein the context-sensitive interrupt instantiation module is to create the interrupt gate entry in the IDT to invoke a context-sensitive local descriptor table record (“

context-sensitive LDT record”

), wherein the context-sensitive interrupt instantiation module is to program the context-sensitive LDT record with a memory segment descriptor, wherein the memory segment descriptor identifies an interrupt service routine (“

ISR”

) code and data of the interrupt.

3. The apparatus according to claim 2, wherein the context-sensitive interrupt instantiation module is to instantiate a plurality of interrupts, wherein at least two of the plurality of interrupts comprise memory segment descriptors, wherein the memory segment descriptors point to a common memory location, wherein the common memory location comprises the ISR code and data of the interrupt, and wherein an integrity of the common memory location is protected by a write access protection.

4. The apparatus according to claim 1, wherein the then-active compartment is one of a compartment of an operating system (“

OS”

) or of a trusted execution environment (“

TEE”

), wherein the compartment uses a memory region of the memory protected by a root of trust, wherein the interrupt is to be invoked directly, without a mutually trusted dispatcher, and wherein the compartment of the OS or of the TEE is to store and retrieve its state in such compartment prior to and upon returning from the interrupt.

5. The apparatus according to claim 1, wherein the interrupt signal comprises a prefix to perform at least one of a clearing a shared resource, a timer, or a memory-mapped input/output register prior to an implementation of the interrupt, wherein the prefix is shared as immutable code across more than one compartment or is customized for each compartment and/or application within each compartment.

6. The apparatus according to claim 1, wherein the context-sensitive interrupt instantiation module is to instantiate the interrupt according to at least one of an application for a trusted execution environment (“

TEE”

) or a TEE loader during initialization of the computer processor.

7. The apparatus according to claim 1, wherein the context-sensitive interrupt instantiation module is to create a context-sensitive local descriptor table (“

LDT”

) record for each compartment, program the interrupt gate entry to point to the context-sensitive LDT record for a then-active compartment, and wherein the context-sensitive interrupt instantiation module is to program the LDT record to perform a far call to an interrupt service routine (“

ISR”

) of an operating system or TEE executed by the computer processor, wherein the far call comprises a task state segment (“

TSS”

) comprising an access and permissions of the ISR of the operating system or TEE and with a startup state to cause the computer processor to inspect the interrupt signal in the shared memory in conjunction with the far call to the ISR of the operating system or TEE.

8. A computer implemented method, comprising:

instantiating an interrupt to interrupt a process of a computer processor by creating a plurality of interrupt dispatch tables (“

IDTs”

), one for each compartment of a computer processor and creating an interrupt gate entry in an IDT of the plurality of the IDTs, wherein the interrupt gate entry is to be resolved at runtime according to a then-active compartment, independent of other compartments, to trigger the interrupt and interrupt the process upon detection of an interrupt signal.

9. The method according to claim 8, wherein creating the interrupt gate entry in the IDT comprising creating the interrupt gate entry in the IDT to invoke a context-sensitive local descriptor table record (“

context-sensitive LDT record”

) and programming the context-sensitive LDT record with a memory segment descriptor, wherein the memory segment descriptor identifies an interrupt service routine (“

ISR”

) code and data of the interrupt.

10. The method according to claim 9, further comprising instantiating a plurality of interrupts, wherein at least two of the plurality of interrupts comprise memory segment descriptors, wherein the memory segment descriptors point to a common memory location, wherein the common memory location comprises the ISR code and data of the interrupt, and wherein an integrity of the common memory location is protected by a write access protection.

11. The method according to claim 8, wherein the then-active compartment is one of a compartment of an operating system (“

OS”

) or of a trusted execution environment (“

TEE”

), and further comprising protecting a memory region used by the compartment with a root of trust, wherein the interrupt is to be invoked directly, without a mutually trusted dispatcher, and wherein the compartment of the OS or of the TEE is to store and retrieve its state in such compartment prior to and upon returning from the interrupt.

12. The method according to claim 8, further comprising creating a context-sensitive LDT for each compartment and programming the interrupt gate to point to the context-sensitive LDT record for a then-active compartment, and programing the LDT record to perform a far call to an interrupt service routine (“

ISR”

) of an operating system or TEE, wherein the far call comprises a task state segment (“

TSS”

) comprising an access and permissions of the ISR of the operating system or TEE and with a startup state to cause the computer processor to inspect the interrupt signal in the shared memory in conjunction with the far call.

13. A system comprising a computer processor, a memory, a hardware exception unit, and an input interface, wherein the system is to:

instantiate an interrupt of a process executed by the computer processor in a compartment, wherein to instantiate the interrupt, the system is to create an interrupt gate entry in an interrupt dispatch table (“

IDT”

), wherein the interrupt gate entry is to be resolved at runtime by the system according to a then-active compartment, independent of other compartments, to trigger the interrupt and interrupt the process upon detection of an interrupt signal by the hardware exception unit.

14. The system according to claim 13, wherein the system is further to create the interrupt gate entry in the IDT to invoke a context-sensitive local descriptor table record (“

context-sensitive LDT record”

), wherein the system is to program the context-sensitive LDT record with a memory segment descriptor, wherein the memory segment descriptor identifies an interrupt service routine (“

ISR”

) code and data of the interrupt.

15. The system according to claim 13, wherein the then-active compartment is one of a compartment of an operating system (“

OS”

) or of a trusted execution environment (“

TEE”

), wherein the compartment uses a memory region of the memory protected by a root of trust, and wherein the interrupt is to be invoked directly, without a mutually trusted dispatcher, wherein the compartment of the OS or of the TEE is to store and retrieve its state in such compartment prior to and upon returning from the interrupt.

16. The system according to claim 13, wherein the interrupt signal comprises a prefix to perform at least one of a clearing a shared resource, a timer, or a memory-mapped input/output register prior to an implementation of the interrupt, wherein the prefix is shared as immutable code across more than one compartment or is customized for each compartment and/or application within each compartment.

17. The system according to claim 13, wherein the system is to instantiate a plurality of interrupts, wherein at least two of the plurality of interrupts comprise memory segment descriptors, wherein the memory segment descriptors point to a common memory location, wherein the common memory location comprises the ISR code and data of the interrupt.

18. The system according to claim 13, wherein the system is to instantiate the interrupt according to at least one of an application for a trusted execution environment (“

TEE”

) or a TEE loader during initialization of the computer processor.

19. The system according to claim 13, wherein the system is to create a context-sensitive local descriptor table (“

LDT”

) record for each compartment, is to program the interrupt gate entry to point to the context-sensitive LDT record for a then-active compartment, and wherein the system is to program the context-sensitive LDT record to perform a far call to an interrupt service routine (“

ISR”

) of an operating system executed by the computer processor, wherein the far call comprises a task state segment (“

TSS”

) comprising an access and permissions of the ISR of the operating system or TEE and with a startup state to cause the computer processor to inspect the interrupt signal in the shared memory in conjunction with the far call to the ISR of the operating system or TEE.

20. One or more computer-readable media comprising instructions that cause a computer device, in response to execution of the instructions by a processor of the computer device, to:

create a plurality of interrupt dispatch tables (“

IDTs”

), one for each compartment of the computer processor; and

create an interrupt gate entry in an IDT of the plurality of the IDTs, wherein the interrupt gate entry is to be resolved at runtime by the computer processor according to a then-active compartment, independent of other compartments, to trigger the interrupt and interrupt the process upon detection of an interrupt signal by a hardware exception unit.

21. The computer-readable media according to claim 20, wherein the instructions are further to cause the computer processor to create the interrupt gate entry in the IDT to invoke a context-sensitive local descriptor table record (“

context-sensitive LDT record”

), wherein the instructions are further to cause the computer processor to program the context-sensitive LDT record with a memory segment descriptor, wherein the memory segment descriptor identifies an interrupt service routine (“

ISR”

) code and data of the interrupt.

22. The computer-readable media according to claim 21, wherein the instructions are further to cause the computer processor to instantiate a plurality of interrupts in more than one of the plurality of IDTs, wherein at least two of the plurality of interrupts comprise memory segment descriptors, wherein the memory segment descriptors point to a common memory location, wherein the common memory location comprises the ISR code and data of the interrupt, and wherein the instructions are further to cause the computer processor to protect an integrity of the common memory location by a write access protection.

23. The computer-readable media according to claim 20, wherein the then-active compartment is one of a compartment of an operating system (“

OS”

) or of a trusted execution environment (“

TEE”

), and wherein the instructions are further to cause the computer processor to protect a memory region of the compartment with a root of trust, and wherein the interrupt is to be invoked directly, without a mutually trusted dispatcher.

24. The computer-readable media according to claim 20, wherein the interrupt signal comprises a prefix and wherein the instructions are further to cause the computer processor to use the prefix at runtime to perform at least one of a clearing of a shared resource, a timer, or a memory-mapped input/output register prior to an implementation of the interrupt, and further comprising wherein the instructions are to cause the computer processor to share the prefix as immutable code across more than one compartment or as customized for each compartment and/or application within each compartment.

25. The computer-readable media according to claim 20, wherein the instructions are further to cause the computer processor to create a context-sensitive local descriptor table (“

LDT”

) record for each compartment, to program the interrupt gate entry to point to the context-sensitive LDT record for a then-active compartment, and to program the LDT record to perform a far call to an interrupt service routine (“

ISR”

) of an operating system or TEE executed by the computer processor, wherein the far call comprises a task state segment (“

TSS”

) comprising an access and permissions of the ISR of the operating system and with a startup state to cause the computer processor to inspect the interrupt signal in the shared memory in conjunction with the call to the ISR of the operating system.