Array Substrate, Display Panel and Test Method Thereof and Display Device

• US 20180286296A1
• Filed: 11/06/2017
• Published: 10/04/2018
• Est. Priority Date: 03/30/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Company Limited (BOE Technology Group Co., Ltd.)
• Inventors: Wang, Xiang, Xu, Wei, Ke, Yu E.
• Granted Patent: US 10,643,513 B2
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G09G 2310/0264 Details of driving circuits
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309

Abstract

An array substrate, a display panel and a test method thereof and a display device. The array substrate has a display region and a peripheral region and includes a first electrode layer and a first test line. The first electrode layer includes a plurality of first signal lines arranged along a first direction, and the first signal lines extend from the peripheral region to the display region; the first test line is provided in the peripheral region, and extends along the first direction; the first test line is overlapped with and insulated from the first signal lines.

Claims

1. An array substrate including a display region and a peripheral region, the array substrate comprising:

a first electrode layer comprising a plurality of first signal lines arranged along a first direction, wherein the first signal lines extend from the peripheral region to the display region; and

a first test line provided in the peripheral region and extending along the first direction, wherein the first test line is overlapped with and insulated from the first signal lines.

2. The array substrate of claim 1, further comprising:

a second electrode layer in a different layer from the first electrode layer and comprising a plurality of second signal lines arranged along the first direction;

wherein the plurality of second signal lines extend from the peripheral region to the display region and arranged alternately with the plurality of first signal lines; and

the first test line is overlapped with and insulated from the second signal lines.

3. The array substrate of claim 2, wherein

the first test line comprises:

a first test electrode provided between two adjacent first signal lines and insulated from the first signal lines; and

a second test electrode provided between two adjacent second signal lines and insulated from the second signal lines;

the first test electrode and the second test electrode are electrically connected to each other to form the first test line.

4. The array substrate of claim 3, further comprising:

a first insulation layer provided between the first electrode layer and the second electrode layer;

wherein the first test electrode and the second test electrode are electrically connected to each other through a via hole in the first insulation layer, to form the first test line.

5. The array substrate of claim 4, further comprising a thin film transistor, wherein

the thin film transistor comprises a gate, a gate insulation layer, a source and a drain;

the first electrode layer is in a same layer as the gate;

the first insulation layer is in a same layer as the gate insulation layer; and

the second electrode layer is in a same layer as the source and the drain.

6. The array substrate of claim 1, wherein

at least one end of the first test line is provided with a test terminal.

7. The array substrate of claim 3, further comprising:

a second test line provided in the peripheral region and extending along the first direction;

wherein the second test line is overlapped with and insulated from the first signal lines.

8. The array substrate of claim 7, wherein the second test line comprises:

a third test electrode provided between two adjacent first signal lines and insulated from the first signal lines and the first test electrode; and

a fourth test electrode provided between two adjacent second signal lines and insulated from the second signal lines and the second test electrode;

wherein the third test electrode and the fourth test electrode are electrically connected to each other to form the second test line.

9. The array substrate of claim 7, wherein

at least one end of the second test line is provided with a test terminal.

10. A display panel, comprising:

the array substrate of claim 1; and

at least one drive circuit;

wherein the at least one drive circuit is electrically connected to a plurality of signal lines of the array substrate and drives the array substrate via the plurality of signal lines.

11. A display device, comprising the display panel of claim 10.

12. A test method of the display panel of claim 10, comprising:

selecting a signal line of the display panel as a signal line to be detected;

short-circuiting the signal line to be detected with the first test line at a position where the signal line to be detected is overlapped with the first test line, and forming a first short-circuit point;

cutting off the signal line to be detected at a side of the first test line far away from the at least one drive circuit; and

obtaining an electrical signal to be analyzed that is outputted from a portion of the at least one drive circuit corresponding to the signal line to be detected, via the first test line and the first short-circuit point, and determining whether or not a defect exists in the portion of the at least one drive circuit corresponding to the signal line to be detected.

13. The test method of claim 12, further comprising:

short-circuiting the signal line to be detected with the second test line at a position where the signal line to be detected is overlapped with the second test line, and forming a second short-circuit point; and

inputting a first signal into the signal line to be detected via the second test line and the second short-circuit point, and determining whether or not the defect exists in a portion of a display panel body corresponding to the signal line to be detected.

14. The test method of claim 12, further comprising:

selecting a signal line corresponding to a normal display area of the display region of the display panel as a reference signal line;

short-circuiting the reference signal line with the first test line at a position where the reference signal line is overlapped with the first test line, and forming a first reference short-circuit point;

cutting off the reference signal line at the side of the first test line far away from the at least one drive circuit;

cutting off the first test line at a position between the first short-circuit point and the first reference short-circuit point;

obtaining a reference electrical signal outputted from a portion of the at least one drive circuit corresponding to the reference signal line, via the first test line and the first reference short-circuit point, and determining whether or not the defect exists in the portion of the at least one drive circuit corresponding to the signal line to be detected by comparing the electrical signal to be analyzed and the reference electrical signal outputted from the at least one drive circuit.

15. The test method of claim 13, further comprising:

selecting a signal line corresponding to a normal display area of the display region of the display panel as a reference signal line;

short-circuiting the reference signal line with the first test line at a position where the reference signal line is overlapped with the first test line, and forming a first reference short-circuit point;

cutting off the reference signal line at the side of the first test line far away from the at least one drive circuit;

cutting off the first test line at a position between the first short-circuit point and the first reference short-circuit point;

obtaining a reference electrical signal outputted from a portion of the at least one drive circuit corresponding to the reference signal line, via the first test line and the first reference short-circuit point, and determining whether or not the defect exists in the portion of the at least one drive circuit corresponding to the signal line to be detected by comparing the electrical signal to be analyzed and the reference electrical signal outputted from the at least one drive circuit.

16. The test method of claim 15, further comprising:

short-circuiting the reference signal line with the second test line at a position where the reference signal line is overlapped with the second test line, and forming a second reference short-circuit point; and

inputting a second signal into the reference signal line via the second test line and the second reference short-circuit point, and determining whether or not the defect exists in the portion of the display panel body corresponding to the signal line to be detected by comparing displayed images in display regions of the display panel body corresponding to the signal line to be detected and the reference signal line.

17. The test method of claim 12, wherein

short-circuiting of the signal line to be detected with the first test line is conducted by laser welding of the signal line to be detected and the first test line.

18. The test method of claim 17, wherein

cutting off the signal line to be detected and/or the first test line is conducted by laser cutting.

19. A test method of the display panel of claim 10, comprising:

selecting a signal line of the display panel as a signal line to be detected;

short-circuiting the signal line to be detected with the first test line at a position where the signal line to be detected is overlapped with the first test line, and forming a first short-circuit point;

cutting off the signal line to be detected at a side of the first test line far away from an array substrate body; and

inputting a first signal into the signal line to be detected, via the first test line and the first short-circuit point, and determining whether or not a defect exists in a portion of a display panel body corresponding to the signal line to be detected.

20. The test method of claim 19, further comprising:

selecting a signal line corresponding to a normal display area of the display region of the display panel as a reference signal line;

short-circuiting the reference signal line with the first test line at a position where the reference signal line is overlapped with the first test line, and forming a first reference short-circuit point;

cutting off the reference signal line at the side of the first test line far away from the array substrate body;

cutting off the first test line at a position between the first short-circuit point and the first reference short-circuit point; and

inputting a second signal into the reference signal line, via the first test line and the first reference short-circuit point, and determining whether or not the defect exists in the portion of the display panel body corresponding to the signal line to be detected by comparing displayed images in display regions of the display panel body corresponding to the signal line to be detected and the reference signal line.