INTEGRATED CIRCUIT IMPLEMENTED INDUCTORS AND METHODS OF MANUFACTURE

• US 20180286556A1
• Filed: 04/01/2017
• Published: 10/04/2018
• Est. Priority Date: 04/01/2017
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jain, Amit K., Shekhar, Sameer, Vu, John T.
• Application Number:
  US15/477,080
• Publication Number:
  US 20180286556A1
• Time in Patent Office: Days
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/002 Details of via holes for interconnecting the layers
• CPC Class Codes: H01F 2017/0073 with a special conductive pattern, e.g. flat spiral
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/00 Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068

Abstract

An inductor of an integrated circuit can include one or more magnetically transparent and non-conductive layers, a plurality of conductive elements, and a plurality of through hole conductor elements. The plurality of conductive elements can be disposed about opposite sides of each of the one or more non-conductive layers. The plurality of through hole conductive elements can be disposed through the one or more non-conductive layers and electrically coupling selected ones of the plurality of conductive elements in one or more conductive paths configured such that a magnetic field generated in response to a current flow in the one or more conductive paths opposes changes in the current flow.

Claims

1. An integrated circuit comprising:

a first non-conductive layer;

a first plurality of conductive elements disposed on a first surface of the first non-conductive layer;

a second plurality of conductive elements disposed on a second surface of the first non-conductive layer opposite the first plurality of conductive elements; and

a third plurality of conductive elements disposed through the first non-conductive layer, wherein a first set of the third plurality of conductive elements are disposed radially from a second set of the third plurality of conductive elements, and wherein the first plurality of conductive elements, the second plurality of conductive elements, and the third plurality of conductive elements are selectively coupled in a first conductive path from sequential alternating ones of the first plurality of conductive elements, the first set of the third conductive elements, the second plurality of conductive elements and the second set of the third conductive elements.

2. The integrated circuit according to claim 1, wherein,

an interconnect passivation layer includes the non-conductive layer;

a first interconnect metalization layer includes the first plurality of conductive elements; and

a second interconnect metalization layer include the second plurality of conductive elements.

3. The integrated circuit according to claim 1, wherein

a semiconductor layer includes the first plurality of conductive elements;

a first insulative layer includes the non-conductive layer; and

a first metal layer includes the second plurality of conductive elements.

4. The integrated circuit according to claim 1, wherein the non-conductive layer includes a glass film.

5. The integrated circuit according to claim 1, wherein the non-conductive layer includes a plastic film.

6. The integrated circuit according to claim 1, wherein the non-conductive layer is magnetically transparent.

7. The integrated circuit according to claim 1, wherein the conductive path is disposed substantially as a toroidal polyhedron.

8. The integrated circuit according to claim 7, wherein a magnetic field generated in response to a current flow in the conductive path is substantially confined to the toroidal polyhedron.

9. The integrated circuit according to claim 7, further including one or more additional conductive elements disposed through the first non-conductive layer in an area surrounded by the toroidal polyhedron.

10. The integrated circuit according to claim 1, further comprising:

a second non-conductive layer;

a fourth plurality of conductive elements disposed on a first surface of the second non-conductive layer;

a fifth plurality of conductive elements disposed on a second surface of the second non-conductive layer opposite the fourth plurality of conductive elements; and

a sixth plurality of conductive elements disposed through the second non-conductive layer, wherein a first set of the sixth plurality of conductive elements are disposed radially from a second set of the sixth plurality of conductive elements, and wherein the fourth plurality of conductive elements, the fifth plurality of conductive elements, and the sixth plurality of conductive elements are selectively coupled in a second conductive path from sequential alternating ones of the fourth plurality of conductive elements, the first set of the sixth conductive elements, the fifth plurality of conductive elements and the second set of the sixth conductive elements; and

wherein the second conductive path is electrically coupled in series or parallel to the first conductive path.

11. An electronic device comprising:

one or more non-conductive layers;

a plurality of conductive elements disposed about opposite sides of each of the one or more non-conductive layers; and

a plurality of through hole conductive elements disposed through the one or more non-conductive layers and electrically coupling selected ones of the plurality of conductive elements in one or more conductive paths configured such that a magnetic field generated in response to a current flow in the one or more conductive paths opposes changes in the current flow.

12. The device according to claim 11, wherein the plurality of through hole conductive elements include a first set of through hole conductive elements disposed in a radial direction from the first set of through hole conductive elements.

13. The device according to claim 12, wherein a width of each of the plurality of conductive elements is substantially uniform in the radial direction.

14. The device according to claim 12, wherein a width of each of the plurality of conductive elements increases in the radial direction, and a spacing between adjacent ones of the plurality of conductive elements in the radially direction is substantially equal.

15. The device according to claim 11, wherein the magnetic field is substantially contained within a toroidal polyhedron bounded by the plurality of conductive elements and the plurality of through hole conductive elements.

16. The device according to claim 15, wherein the magnetic field substantially contained within the toroidal polyhedron is orientated in an x-y plane of the device.

17. The device according to claim 15, wherein the magnetic field substantially contained within the toroidal polyhedron is orientated in an y-z plane of the device.

18. The device according to claim 11, wherein,

the one or more non-conductive layers correspond to one or more passivation layers of an integrated circuit die;

and

the plurality of conductive elements are disposed in one or more semiconductor or metal layers of an integrated circuit die.

19. The device according to claim 11, wherein,

the one or more non-conductive layers correspond to one or more passivation layers of an integrated circuit package;

and

the plurality of conductive elements are disposed in one or more metal layers of an integrated circuit package.

20. The device according to claim 11, wherein the plurality of conductive elements include:

a first conductive layer an in integrated circuit package; and

a second conductive layer in a printed circuit board (PCB), wherein the second conductive layer is electrically coupled to the first conductive layer by a plurality of solder balls or package connection pins.

21. The device according to claim 11, wherein the plurality of conductive elements include:

a first conductive layer in a first integrated circuit; and

a second conductive layer a second integrated circuit, wherein the first and second integrated circuits are electrically coupled to together in a package by a plurality of solder balls or micro-bumps.

22. The device according to claim 11, wherein one or more of the plurality of conductive elements comprise closed loop traces.

23. A method of manufacture comprising:

depositing a first conductive layer on one or more other layers of an integrated circuit;

patterning the first conductive layer to form a first plurality of conductive elements;

depositing one or more non-conductive layers on the first plurality of conductive elements;

forming a plurality of openings through the one or more non-conductive layers to expose selected portions of each of the first plurality of conductive elements;

depositing a second plurality of conductive elements in the opening through the one or more non-conductive layers and electrically coupled to the exposed selected portions of each of the first plurality of conductive elements;

depositing a second conductive layer on an exposed one of the one or more non-conductive layers;

patterning the second conductive layer to form a third plurality of conductive elements selectively coupled to the second plurality of conductive elements; and

wherein the first plurality of conductive elements, the second plurality of conductive elements, and the third plurality of conductive elements are coupled together as a conductive path wrapped about a toroidal polyhedron wherein a first set of the second plurality of conductive elements are disposed about a first perimeter of the toroidal polyhedron and a second set of the second plurality of conductive elements are disposed about a second perimeter of the toroidal polyhedron.

24. The method of manufacturing according to claim 23, wherein,

the one or more layers of the integrated circuit comprise an integrated circuit die;

the first conductive layer is further patterned to form one or more other conductive elements of the integrated circuit die; and

the second conductive layer is further patterned to form one or more additional conductive elements of the integrated circuit die.

25. The method of manufacturing according to claim 23, wherein,

the one or more layers of the integrated circuit comprise an integrated circuit package;

the first conductive layer is further patterned to form one or more other conductive elements of the integrated circuit package; and

the second conductive layer is further patterned to form one or more additional conductive elements of the integrated circuit package.

26. The method of manufacturing according to claim 23, wherein,

the one or more layers of the integrated circuit comprises an integrated circuit die;

the first conductive layer is further patterned to form one or more other conductive elements of the integrated circuit die; and

the second conductive layer is further patterned to form one or more additional conductive elements of the integrated circuit package.

27. The method of manufacturing according to claim 23, wherein

the one or more non-conductive layers include one or more glass film layers;

the first conductive layer includes a first metal layer; and

the second conductive layer includes a second metal layer.

28. An integrated circuit comprising:

a first inductor including,

a first non-conductive layer;

a first plurality of conductive elements disposed on a first surface of the first non-conductive layer;

a second plurality of conductive elements disposed on a second surface of the first non-conductive layer opposite the first plurality of conductive elements; and

a third plurality of conductive elements disposed through the first non-conductive layer, wherein the first plurality of conductive elements, the second plurality of conductive elements, and the third plurality of conductive elements are selectively coupled in a first conductive path bounding a toroidal polyhedron portion of the first non-conductive layer from sequential alternating ones of the first plurality of conductive elements, the first set of the third conductive elements, the second plurality of conductive elements and the second set of the third conductive elements; and

a second inductor of a spiral type inductor, a figure-eight type inductor or a race track type inductor.

29. The integrated circuit according to claim 28, wherein a magnetic field generated in response to a current flow in the conductive path of the first inductor is substantially confined to the toroidal polyhedron.