Method and Device for Electrical Overstress and Electrostatic Discharge Protection

• US 20180286854A1
• Filed: 03/19/2018
• Published: 10/04/2018
• Est. Priority Date: 03/28/2017
• Status: Active Grant

• Current Assignee: Semtech Corporation
• Original Assignee: Semtech Corporation
• Inventors: Rose, David J., Russell, William A., Clark, Jonathan
• Granted Patent: US 10,692,854 B2
• Time in Patent Office: Days
• CPC Class Codes: H01C 7/12 Overvoltage protection resistors series resistors structurally associated with spark gaps H01T1/16
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H02H 9/025 Current limitation using field effect transistors
• CPC Class Codes: H02H 9/041 using a short-circuiting device
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

Claims

1. A semiconductor device, comprising:

a signal source;

a load;

a transmission line coupled between the signal source and load;

a series protection circuit electrically coupled in series along the transmission line between the signal source and the load, wherein the series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load; and

a parallel protection circuit electrically coupled between the transmission line and a ground node.

2. The semiconductor device of claim 1, wherein the series protection circuit further includes a second FET and third FET coupled in series with the first FET between the signal source and load.

3. The semiconductor device of claim 2, wherein the series protection circuit further includes a fourth FET coupled in series with the first FET, second FET, and third FET between the signal source and load.

4. The semiconductor device of claim 1, wherein a gate terminal of the first FET is coupled to a signal source end of the transmission line or a load end of the transmission line.

5. The semiconductor device of claim 1, wherein the series protection circuit further includes a diode and resistor coupled in series between the signal source and a gate terminal of the first FET.

6. The semiconductor device of claim 1, wherein the parallel protection circuit includes a transient-voltage-suppression (TVS) diode.

7. A semiconductor device, comprising:

a signal source;

a load;

a series protection circuit electrically coupled in series between the signal source and the load; and

a parallel protection circuit electrically coupled between the load and a ground node.

8. The semiconductor device of claim 7, wherein the series protection circuit includes a first field-effect transistor (FET) and the parallel protection circuit includes a transient-voltage-suppression (TVS) diode.

9. The semiconductor device of claim 8, wherein the series protection circuit further includes a second FET electrically coupled in series with the first FET between the signal source and load.

10. The semiconductor device of claim 9, wherein a source terminal of the first FET is coupled to a source terminal of the second FET.

11. The semiconductor device of claim 10, wherein a gate terminal of the first FET is coupled to the signal source and a gate terminal of the second FET is coupled to the load.

12. The semiconductor device of claim 9, wherein the series protection circuit further includes:

a first diode coupled between the signal source and a gate terminal of the second FET; and

a second diode coupled between the load and the gate terminal of the second FET.

13. The semiconductor device of claim 7, wherein the series protection circuit includes a field-effect transistor (FET) and resistor coupled in series between the signal source and load.

14. A method of protecting a semiconductor device from electrical overstress (EOS) and electro-static discharge (ESD) events, comprising:

providing a series protection circuit electrically coupled in series between the semiconductor device and a signal source, wherein the series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load; and

providing a parallel protection circuit electrically coupled between the series protection circuit and a voltage node.

15. The method of claim 14, wherein providing the series protection circuit includes providing a second FET coupled in series with the first FET between the signal source and load.

16. The method of claim 15, wherein providing the series protection circuit further includes providing a third FET and fourth FET coupled in series with the first FET and second FET between the signal source and load.

17. The method of claim 15, further including:

coupling a gate terminal of the first FET to the signal source; and

coupling a gate terminal of the second FET to the load.

18. The method of claim 14, wherein providing the series protection circuit further includes:

providing a diode coupled between the signal source and a gate terminal of the first FET; and

providing a resistor coupled between the signal source and a gate terminal of the first FET.

19. The method of claim 14, wherein providing the parallel protection circuit includes providing a transient-voltage-suppression (TVS) diode.

20. A method of making a semiconductor device, comprising:

providing a series protection circuit electrically coupled in series between a signal source and signal destination of the semiconductor device; and

providing a parallel protection circuit electrically coupled to the series protection circuit.

21. The method of claim 20, wherein providing the series protection circuit includes providing a first field-effect transistor (FET), and providing the parallel protection circuit includes providing a transient-voltage-suppression (TVS) diode.

22. The method of claim 21, wherein providing the series protection circuit further includes providing a second FET electrically coupled in series between the signal source and signal destination.

23. The method of claim 22, further including coupling a source terminal of the first FET to a source terminal of the second FET.

24. The method of claim 23, further including coupling a gate terminal of the first FET to the signal source and a gate terminal of the second FET to the signal destination.

25. The method of claim 22, wherein providing the series protection circuit further includes coupling a first diode and resistor in series between the signal source and a gate terminal of the second FET.