SEMICONDUCTOR APPARATUS AND EQUIPMENT HAVING LAMINATED LAYERS

• US 20180286910A1
• Filed: 03/22/2018
• Published: 10/04/2018
• Est. Priority Date: 03/30/2017
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Kobayashi, Masahiro
• Granted Patent: US 10,453,888 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures

Abstract

In a semiconductor apparatus including: a semiconductor substrate in which a plurality of semiconductor elements are provided; a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided; a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer; a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer; a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, widths of a plurality of through electrodes are different from each other.

Claims

1. A semiconductor apparatus comprising:

a semiconductor substrate in which a plurality of semiconductor elements are provided;

a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided;

a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer;

a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer;

a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and

a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, wherein;

the first semiconductor layer includes a first main surface on a side of the first wiring structure;

the first wiring structure includes a first wiring;

the second semiconductor layer includes a second main surface on a side of the second wiring structure;

the second wiring structure includes a second wiring;

the third wiring structure includes a third wiring;

a through electrode that passes through the first semiconductor layer and reaches the first wiring; and

a through electrode that passes through the second semiconductor layer and reaches the third wiring are further included, and

a width, on the first main surface, of the through electrode reaching the first wiring is different from a width, on the second main surface, of the through electrode reaching the third wiring.

2. The semiconductor apparatus according to claim 1, wherein:

the third wiring is electrically connected to the first wiring;

the third wiring structure includes a fourth wiring that is electrically connected to the second wiring; and

the width, on the first main surface, of the through electrode reaching the first wiring is narrower than the width, on the second main surface, of the through electrode reaching the third wiring.

3. The semiconductor apparatus according to claim 1, wherein:

the third wiring is electrically connected to the first wiring;

the third wiring structure includes a fourth wiring that is electrically connected to the second wiring; and

the width, on the first main surface, of the through electrode reaching the first wiring is wider than the width, on the second main surface, of the through electrode reaching the third wiring.

4. The semiconductor apparatus according to claim 1, wherein the through electrode reaching the first wiring connects a pixel circuit unit that is constituted by the first wiring structure and the first semiconductor layer and a column circuit unit that is constituted by the third wiring structure and the semiconductor substrate.

5. The semiconductor apparatus according to claim 1, wherein the through electrode reaching the first wiring is overlapped on the through electrode reaching the third wiring.

6. The semiconductor apparatus according to claim 1, wherein the second semiconductor layer and the second wiring structure constitute a DRAM cell array.

7. The semiconductor apparatus according to claim 1, wherein a thickness of the second semiconductor layer is thicker than a thickness of the first semiconductor layer and thinner than a thickness of the semiconductor substrate.

8. The semiconductor apparatus according to claim 1, wherein a thickness of the semiconductor substrate is greater than twice of a distance from the semiconductor substrate to a surface of the first semiconductor layer, which is opposite to the first main surface, and smaller than 20 times of the distance.

9. Equipment comprising:

the semiconductor apparatus according to claim 1, wherein at least one of an optical system that forms an image in the semiconductor apparatus, a control apparatus that controls the semiconductor apparatus, a processing apparatus that processes a signal output from the semiconductor apparatus, a display apparatus that displays information obtained by the semiconductor apparatus, and a memory apparatus that stores information obtained by the semiconductor apparatus is further included.

10. The semiconductor apparatus according to claim 1, wherein:

the third wiring is electrically connected to the second wiring; and

the third wiring structure includes a fourth wiring that is electrically connected to the first wiring.

11. The semiconductor apparatus according to claim 10, wherein the width, on the first main surface, of the through electrode reaching the first wiring is narrower than a width, on the second main surface, of a through electrode reaching the fourth wiring.

12. The semiconductor apparatus according to claim 10, wherein the width, on the first main surface, of the through electrode reaching the first wiring is wider than a width, on the second main surface, of a through electrode reaching the fourth wiring.

13. The semiconductor apparatus according to claim 10, wherein the third wiring structure includes a fifth wiring that is connected to a pad included in the first wiring structure, a through electrode that passes through the second semiconductor layer and reaches the fifth wiring is further included, and a width, on the second main surface, of the through electrode reaching the fifth wiring is wider than the width, on the first main surface, of the through electrode reaching the first wiring.

14. The semiconductor apparatus according to claim 10, wherein:

the first semiconductor layer includes a pixel region in which the plurality of photoelectric conversion elements are arrayed; and

a through electrode reaching the fourth wiring is arranged between the pixel region and the semiconductor substrate.

15. The semiconductor apparatus according to claim 10, wherein the third wiring structure includes a fifth wiring that is connected to a pad included in the first wiring structure, a through electrode that passes through the second semiconductor layer and reaches the fifth wiring is further included, and a width, on the second main surface, of the through electrode reaching the fifth wiring is wider than a width, on the second main surface, of a through electrode reaching the fourth wiring.

16. A semiconductor apparatus comprising:

a semiconductor substrate in which a plurality of semiconductor elements are provided;

a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided;

a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer;

a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer;

a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and

a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, wherein;

the first semiconductor layer includes a first main surface on a side of the first wiring structure;

the first wiring structure includes a first wiring and a second wiring;

the second semiconductor layer includes a second main surface on a side of the second wiring structure;

the third wiring structure includes a third wiring that is electrically connected to the first wiring and a fourth wiring that is electrically connected to the second wiring;

a through electrode that passes through the first semiconductor layer and reaches the first wiring; and

a through electrode that passes through the first semiconductor layer and reaches the second wiring are included, and

a width, on the first main surface, of the through electrode reaching the first wiring is different from a width, on the first main surface, of the through electrode reaching the second wiring.

17. The semiconductor apparatus according to claim 16, wherein the width, on the first main surface, of the through electrode reaching the first wiring is narrower than the width, on the first main surface, of the through electrode reaching the second wiring.

18. The semiconductor apparatus according to claim 16, wherein the width, on the first main surface, of the through electrode reaching the first wiring is wider than the width, on the first main surface, of the through electrode reaching the second wiring.

19. The semiconductor apparatus according to claim 16, wherein a distance between a through electrode, a width on the first main surface of which is wider of the through electrode reaching the first wiring and the through electrode reaching the second wiring, and an outer edge of the semiconductor layer is shorter than a distance between a through electrode a width on the first main surface of which is narrower and the outer edge of the semiconductor layer.

20. A semiconductor apparatus comprising:

a semiconductor substrate in which a plurality of semiconductor elements are provided;

a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided;

a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer;

a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer;

a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and

a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, wherein;

the first semiconductor layer includes a first main surface on a side of the first wiring structure;

the first wiring structure includes a first wiring;

the second semiconductor layer includes a second main surface on a side of the second wiring structure;

the second wiring structure includes a second wiring;

the third wiring structure includes a third wiring that is electrically connected to the first wiring and a fourth wiring that is electrically connected to the second wiring;

a through electrode that passes through the second semiconductor layer and reaches the third wiring; and

a through electrode that passes through the second semiconductor layer and reaches the fourth wiring are included, and

a width, on the second main surface, of the through electrode reaching the third wiring is different from a width, on the second main surface, of the through electrode reaching the fourth wiring.

21. The semiconductor apparatus according to claim 20, wherein the width, on the second main surface, of the through electrode reaching the third wiring is wider than the width, on the second main surface, of the through electrode reaching the fourth wiring.

22. The semiconductor apparatus according to claim 20, wherein the width, on the second main surface, of the through electrode reaching the third wiring is narrower than the width, on the second main surface, of the through electrode reaching the fourth wiring.

23. The semiconductor apparatus according to claim 20, wherein a distance between a through electrode, a width on the second main surface of which is wider of the through electrode reaching the third wiring and the through electrode reaching the fourth wiring, and an outer edge of the semiconductor layer is shorter than a distance between a through electrode a width, on the second main surface, of which is narrower and the outer edge of the semiconductor layer.

24. Equipment that includes a machine apparatus, further comprising:

the semiconductor apparatus according to claim 20; and

a processing apparatus that performs, on a basis of information obtained by the semiconductor apparatus, processing for operating the machine apparatus.